Design for Manufacturability: New Problems for VLSI Physical Design

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Design for ManufacturabilityNew Problems for
VLSI Physical Design

• Patrick H. Madden
• SUNY Binghamton CSDpmadden_at_acm.org

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Outline

• Brief Overview of Lithography
• What does DFM mean?
• Traditional Circuit Routing
• What's Changed
• Lithographic impact on routing
• New routing ideas
• Whats Next
• Custom design at 90nm
• Few designs at 65nm and below (only MPUs, FPGAs,
  memory, and maybe high volume structured ASICs)

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Silicon Devices
Assorted pictures from Google
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Lithography
Assorted pictures from Google
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What is DFM?

• Avoid designing things that
• Will look blurred during lithography
• Blur means the wires will be larger/smaller than
  you wanted
• Possible shorts, opens,
• Make the surface of the chip uneven
• The focus range of litho is very small an uneven
  surface for projection results in distortion.
• The surface of the chip has to be polished for
  each layer an uneven surface results in
  dishing, where high points might be worn off,
  while low points are not touched.
• Will have dramatic performance changes if the
  chip doesnt exactly match the design
• Especially for 65nm and below, different
  transistors on different parts of the die may
  operate faster/slower.
• Transistor orientation can change performance.

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DFM is Not New

• Antenna Fixing
• Jumpers (or bridges) break long wire
• Diodes introduce diffusion

G
jumper
G
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Conventional Routing

• Assume we have the logic elements placed
• Connecting the nets
• NP-Hard (Steiner problem), but essentially solved
• Connecting each pair of pins is almost always
  Rip-up and Reroute (with the routing done by
  Dijkstra's algorithm)

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Problem Formulation

• Over-the-cell, graph-based router
• G (V, E)
• Edge e(ij) from node i to node j has capacity
  c(ij) and usage u(ij).
• Usage number of nets using e(ij).
• Congestion u(ij) / c(ij)
• If u(ij) gt c(ij), the edge is over congested or
  overflown

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Basic Routing Approach

• Decomposes nets into 2 pin connections (wires)
  using a Steiner heuristic
• Initial routing of each wire using efficient
  implementation of Dijkstra shortest path
  algorithm
• Every wire is then rerouted during rip and
  reroute iterations
• Rip and reroute phase ends after a specified
  number of iterations, or when results converge

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Basic Routing Algorithm

• steiner_decompose (netlist N)
• route (wirelist W)
• for (n iterations)
• for (wirelist W)
• remove_path (wire w)
• find_shortest_path (wire w)
• add_path (wire w)
• end
• end

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Linear Cost Function (Linsker)

• Use a linearly increasing cost function
• As the congestion of an edge e(ij) increases, the
  cost of using e(ij) increases (the maze router
  computes the cost for every edge it considers)
• Full reroute plus linear cost function create
  erosion of congested peaks of routing surface

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Detail Routing

• In some respects, similar to global
• Dijkstra's algorithm is the heart of many tools
• Channel routing techniques are still sometimes
  used
• Define the routing surface as a graph run RR
• Gridless routing is much harder not clear how
  much benefit it provides

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Detail Routing
Slides from Hardy Leung (Magma)/ISPD03
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Whats Changed?

• DFM issues have made the routing problem much
  more difficult. Dijkstras algorithm breaks down
  under modern lithography.
• Dijkstra's algorithm finds the shortest path
  when...
• d(j) min(d(j), d(i) cost of e(i j))
• Simple greedy algorithm, well known efficient
  implementation, optimal solutions to this
  problem.
• Only now, how we calculate d(j) has changed

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Slides from Lars Liebmann, ISPD03/IBM
Slides by Lars Liebmann/IBM (ISPD03)
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The Ideal Chip Design
Odd metal layers
Even metal layers
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Detail Routing
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Evolution of Spacing Rules

• Per-layer constant
• Fatwire spacing
• Special spacing for very fat wire (20X minimum
  width)
• Power grid location may change the spacing for
  the routing (some grids now use filleting)
• Width-dependent spacing
• Spacing is expressed as a function of max(W1, W2)
  
• WL-dependent spacing
• Spacing is expressed as a function of L, max(W1,
  W2)
• Routing direction may change the accepted width

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Complex Spacing Rules (cont.)

• Case I Notch Filling
• Need polygon-based fatwire analysis with halo
• Actual violation is far away from the notch

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Complex Spacing Rules (cont.)

• Case III Fatwire Created During Routing
• Individual wires and vias look clean
• Not if combined

M6
M6
0.9u
M5
M5
0.9u
1.8u
M4
M4
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Redundant Vias

• Single-cut via ? Double-cut via
• Improve yield and reliability
• Based on post-processing

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OPC- and PSM-Aware Routing

• Direction-dependent Width and Spacing

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Detail Routing
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No Longer WYSIWYG

• What you want on silicon may not look like what
  you need on the mask
• What you can (and cannot have) depends a great
  deal on the optics
• Design rule books are exploding in size
• The simple Lambda-rules of MC are gone
• Catch-22 on the rule books themselves the
  process is being tuned while the rules are being
  written!

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So how do we deal with all of this?
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DFM issues for Global Routing

• Even routing distribution results in more
  balanced metalization
• Less need for dummy fill
• Current Challenge
• Balance the number of bends, layer utilization,
  and routing density
• Forbidden pitch makes this more interesting
• There may be different levels of congestion that
  are desirable!

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Detail Routing The Real Challenge

• All the lithographic constraints become difficult
  in DR
• Dijkstra's algorithm no longer applies
• Individual routes have very complex interactions
• Note few academic groups are working on detail
  routing
• About five that Im aware of -- in contrast to
  20 groups publishing regularly on circuit
  placement
• Detail routing is an order of magnitude harder
  than placement.
• There is a serious lack of benchmarks for
  routing, making this area even more difficult to
  operate in

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Detail Routing
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New Detail Routing IdeasCurrent research effort

• Enumerate multiple possible routes for each
  connection
• Restricted Design Rule based
• Design rule violations are allowed at this stage!
• Remove excess routes to find a compatible set.
• Why is this better?
• Routes can be generated by design-rule-correct
  methods. No need to evaluate cost on-the-fly, as
  with Dijkstra
• Allows for more complex objective functions, and
  preference for more manufacturable layout (rather
  than just binary design rule compliance)

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Some Quick Definitions

• Route a way to get from point A to A
• Bundle a set of different routes from A to A
• Candidate Route one element in a bundle
• Constraint Graph each candidate is represented
  by a vertex, while design rule violations between
  candidates are represented by edges.
• Costs are assigned to edges and vertices.

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Example
A
B
A
Design rule violation Crosstalk problem
B
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Example
A
2
B
2
1
1
4
3
3
4
A
Design rule violation Crosstalk problem
B
Remove route 4 as it causes the most violations
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Example
A
2
B
2
1
1
4
3
3
4
A
Design rule violation Crosstalk problem
B
Remove route 4 as it causes the most
violations Remove route 2 as it causes a
crosstalk problem
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Current Routing Tool
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How Effective is DFM?

• By considering lithographic effects, we should be
  able to improve yield and lower costs.
• But by how much?
• I have no idea.
• Neither does anyone else outside of the foundry
  (and they might not know either).
• We should hire the KGB or the mafia to steal fab
  data -- Lou Scheffer (Cadence)

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Three Ways to do Design

• Accurate Modeling
• Requires fab data, and will be very complex.
  Only recommended for those who own the fab lines.
• Restricted Design Rules (IBM)
• Only parallel wires, uniform spacing and width.
  No bends So simple and restricted that it poses
  no DFM problems.
• Structured ASIC and FPGA
• Transistors and routing are designed (by those
  who one the fab lines). Connections are made
  through e-beam cuts.

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What's next?

• DFM issues may kill conventional custom design
  (below 90nm)
• Few tools can really support this complexity
• Tuning the tools requires knowing the foundry
  process this information is currently
  proprietary.
• An opportunity find a way to optimize for DFM
  effectively (and in a generic manner).
  KLA-Tencor has an encrypted software model that
  may provide enough information for physical
  design tools.
• 65nm and lower?
• Microprocessors and memory
• FPGAs
• Structured ASICs?

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Structured ASICs

• FPGA-like regularity makes the physical design
  easy
• Program with e-beam cuts for the vias
• Eliminates the hassle of DFM (for the end user)
• Performance?? Price??

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Restricted Design Rules

• Pushed by IBM
• All wires on a layer are uniformly spaced, and in
  the same direction
• Restrictions on via locations, ....
• Simplifies the rules considerably lets the
  process be heavily tuned

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Improving the Results

• steiner_decompose (netlist N)
• weight_graph (graph G, strength S)
• route (wirelist W)
• for (n iterations)
• weight_graph (graph G, strength S)
• for (wirelist W)
• remove_path (wire w)
• find_shortest_path (wire w)
• add_path (wire w)
• end
• end

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A Priori Congestion Estimation

• The weight_graph function adds congestion to the
  graph, forcing wires to avoid congested areas
• Before the initial routing, a probabilistic
  estimation technique is used to predict areas of
  high congestion
• The congestion estimate is amplified and added to
  the routing surface
• The added congestion is removed after routing pass

Left congestion estimation for ibm01 Right
amplified congestion estimation for ibm01
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Note the problem is 3D
Current research effort incorporate via costs
better. Vias (and bends in general) lower yield.
Open question -- how to reduce congestion while
avoiding bend?