ECE U322 Digital Logic Design

1
ECE U322Digital Logic Design
Oct. 24, 2005

• Lecture 19
• Latches and Flipflops
• Reading Marcovitz 6.2
• Homework 5 due October 27

2
Combinational Logic

• Inputs change gt outputs change
• I can determine what the output is by knowing the
  current inputs
• I dont need any other information

3
Sequential Logic

• Sequential Logic
• Combinational Logic Memory
• Why do we need memory ?
• Combinational logic
• can add two numbers. But
• No way of adding two numbers, then adding a third
  (a sequential operation)
• No way of remembering or storing information
  after inputs have been removed.

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Sequential Circuits Get memory through
feedback Outputs of circuit feed back to
inputs
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Latches

• Latches are the simplest memory elements
• A latch stores one bit of data
• Latches are built from logic gates
• Get memory with feedback
• connect outputs back to inputs

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SR Latch Set Reset Latch
S and R inputs are active low
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SR-latch Setting the latch
8
SR-latch Resetting the latch
9
SR-latch No change
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SR-latch

• Two steady states
• Storing 0 Q 0, Q 1
• Storing 1 Q 1, Q 0
• S sets the latch. R resets the latch.
• What if I assert S and R at the same time ?

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SR-latch Assert S and R

• S 0, R 0, Q 1 and Q 1
• Let S 1 and R 1 what happens ?

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SR-latch Assert S and R

• S 0 and R 0, output is defined
• Q and Q are not the negation of one another
• After, if you set both S 1 and R 1
• Q and Q are in an unknown state
• S 0 and R 0 is called unallowed
• Do not let designer use this combination of
  inputs

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SR latch truth table
S R Q Q
0 0 0 1 1 0 1 1
1 1 Unallowed
1 0 Set
0 1 Reset
Qp Qp

• Store

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SR Latch Set Reset Latch
S
Q
Q
R
15
SR latch truth table
S R Q Q
0 0 0 1 1 0 1 1
Qp Qp Store
0 1 Reset
1 0 Set
Unallowed
0 0
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SR Latch Timing
Set
Reset
Clock
Q
(b)
Figure 6.4
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S-R Latch with control input

• Sometimes, want to avoid latch changes
• C 0 disables all latch state changes
• Control signal enables data change C 1
• Right side of circuit same as ordinary S-R latch

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D Latch

• Q0 indicates the previous state (the previously
  stored value)

X
S
Q
C
Q
R
Y
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D Latch
X
S
D
Q
C
Q
R
Y

• Input value D is passed to output Q when C
  is high
• Input value D is ignored when C is low

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D Latch
Latches on falling edge of clock
E
x

• Z only changes when E is high
• If E is high, Z will follow X
• This behavior is called transparent or level
  sensitive

21
D Latch
Latches on falling edge of clock
E
x

• The D latch stores data indefinitely, regardless
  of input D values, if C 0
• Forms basic storage element in computers

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Sequential Circuit Models

• Outputs depend on inputs and on present state
• history of circuit is captured in present
  state
• Outputs are
• next state function what next state will be
• There may be other outputs
• for latches and flipflops output is the
  present state

23
Sequential Circuits Get memory through
feedback Outputs of circuit feed back to
inputs
Present state
Next state
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Sequential Circuit Models

• New ways to describe sequential circuits
• State Table
• like Truth Table, present state is an input
• Characteristic (or State) Equation
• similar to Boolean equation
• State Diagram

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State Table

• State table gives output, next state as function
  of inputs, present state

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Can abbreviate table

• Use input dont cares

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Characteristic Equation

• Like Boolean logic equation
• output is function of inputs
• now inputs are S, R and Q, output is Q
• Captures behavior of SR latch

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State Diagram

• Bubble represents a state
• Arc between bubbles represents a state transition
• Arc is labelled with inputs that cause state
  transition

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State Diagram for SR latch

• SR latch has 2 states
• storing a 0, storing a 1
• S and R inputs can each be 0 or 1.
• Do not show the S 1, R 1 case

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SR Latch Q S RQ