Computer Architecture and Organization

1
Computer Architecture and Organization

• Ben Juurlink Module 3
• Delft University of Technology Instructions
  Language of the
• April - May 2001 Machine

2
Objectives

• After this lecture, you should be able to
• translate C statements to MIPS assembly code
• translate more complex stuff to assembly code,
  like
• while loop
• for loop
• switch statement
• (recursive) functions
• tell what a stack is and what it is used for in
  the MIPS architecture
• translate MIPS assembly instructions to machine
  code and vice versa
• describe the meaning of the following terms
  alignment, little and big endian, stored program
  concept, ASCII, linker, addressing mode

3
Instructions

• Language of the Machine
• More primitive than higher level languages e.g.,
  no sophisticated control flow
• Very restrictive e.g., MIPS arithmetic
  instructions have 3 register
• operands
• Well be working with the MIPS instruction set
  architecture
• similar to other architectures developed since
  the 1980's
• used by NEC, Nintendo, Silicon Graphics, Sony
• Design goals maximize performance and minimize
  cost, reduce design time, reduce energy
  consumption

4
Types of Instructions

• Arithmetic
• Integer
• Floating Point
• Memory access instructions
• Load Store
• Control flow
• Jump
• Conditional Branch
• Call Return

5
Arithmetic Instructions

• Most instructions have 3 operands
• Operand order is fixed (destination first)
• Operands are registers
• Example C code A B C MIPS code add
  s0, s1, s2 (s0, s1 and s2 are
  register which the compiler (or assembly
  programmer) associates with variables)

6
Arithmetic Instructions

• Design Principle simplicity favors regularity.
  Why?
• Of course this complicates some things... C
  code A B C D E F - A MIPS
  code add t0, s1, s2 add s0, t0,
  s3 sub s4, s5, s0
• Operands must be registers, only 32 registers
  provided
• Design Principle smaller is faster. Why?

7
Registers vs. Memory

• Arithmetic instructions operands must be
  registers, only 32 registers provided
• Compiler associates variables with registers
  (register allocation)
• What about programs with lots of variables (large
  arrays, aliasing)?

8
Memory Organization

• Can be viewed as a large, one-dimension array of
  bytes
• A memory address is an index into the array
• "Byte addressing" means that the index points to
  a byte of memory.

9
Memory Organization

• Bytes are nice, but most data items use larger
  "words"
• For MIPS, a word is 32 bits or 4 bytes (registers
  are also 32 bits)
• Thus, memory can be viewed as
• an array of bytes with addresses 0, 1, 2, 3,
• an array of words with addresses 0, 4, 8, 12, ...

Registers hold 32 bits of data
...
10
Memory layout Alignment

• Words are aligned, i.e., they start at addresses
  which are a multiple of 4 (what are the least 2
  significant bits of a word address?)
• Processors number bytes within a word in two
  different ways
• Big Endian most significant byte comes first
  (MIPS)
• Example 0xaabbccdd
• Little Endian least significant byte comes first
  (x86/Pentium)

11
Data Transfer Instructions

• Load and store instructions
• Example C code int h, A100
• A10 h A8 MIPS code lw t0,
  32(s3) add t0, s2, t0 sw t0,
  40(s3)
• Note store word has destination last
• Remember arithmetic operands are registers, not
  memory

12
Bigger Example

• Can you figure out the code?

int temp, k, v100, temp vk vk
vk1 vk1 temp
add t0,a1,a1 add t0,t0,t0 add t0,t0,a0 lw
t1,0(t0) lw t2,4(t0) sw t2,0(t0) sw t1
,4(t0)
Explanation index k a1 base address of
v a0 address of vk is a0 4a1
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Summary

• MIPS
• loading words but addressing bytes
• words are aligned
• big endian
• arithmetic on registers only
• Instruction Meaningadd s1, s2, s3
  s1 s2 s3sub s1, s2, s3 s1 s2
  s3lw s1, 100(s2) s1 Memorys2100 sw
  s1, 100(s2) Memorys2100 s1

14
Machine Language

• Instructions are also 32 bits long
• Registers have numbers t08, s117, s218
• Example add t0, s1, s2
• Instruction Format 000000 10001 10010
  01000 00000 100000 op rs rt rd
  shamt funct
• Can you guess what the field names stand for?

15
Machine Language

• Consider the load-word and store-word
  instructions
• What would the regularity principle have us do?
• New principle Good design demands a compromise
• Introduce a new type of instruction format
• I-type for data transfer instructions
• other format was R-type for register
• Example lw t0, 32(s2) 35 18 9
  32 op rs rt 16 bit number
• Where's the compromise?
• Study example on page 119-120

16
Stored Program Concept

• Instructions are bits
• Programs are stored in memory to be read or
  written just like dataFetch Execute
  Cycle
• Instructions are fetched and put into a special
  register
• Bits in the register "control" the subsequent
  actions
• Fetch the next instruction and continue

memory for data, programs, compilers, editors,
etc.
Processor
Memory
17
Stored Program Concept
memory
OS
code
Program 1
data
CPU
unused
Program 2
unused
18
Control Instructions

• Decision making instructions
• alter the control flow,
• i.e., change the "next" instruction to be
  executed
• Two types
• conditional branch instructions
• unconditional branch instructions (jump)

19
Control Instructions

• MIPS conditional branch instructions bne t0,
  t1, Label beq t0, t1, Label
• Example if (ij) h i j bne s0,
  s1, Label add s3, s0, s1 Label ....

20
Control Instructions

• MIPS unconditional branch instruction j label
• Example if (i!j) bne s4,s5,then
• hij sub s3,s4,s5 else j fi
• hi-j then add s3, s4,
  s5 fi ...
• Can you build a simple for loop?

21
For Loops

• C code
• for (i0 i ! n i ik)
• a ab
• Assembly
• add t0, zero, zero it00
• Loop
• beq t0, s0, Exit if (in) goto Exit
• add s1, s1, s2 a ab
• add t0, t0, t1 i ik
• j Loop goto Loop
• Exit
• Active learning try using only one branch
  instruction per loop iteration

22
While Loops

• C code
• while (saveik)
• i ij
• Assembly code
• Loop add t1, s3, s3
• add t1, t1, t1
• add t1, t1, s6
• lw t0, 0(t1)
• bne t0, s5, Exit
• add s3, s3, s4
• j Loop
• Exit ...

23
Addresses in Branches

• Instructions
• bne t4,t5,Label Next instruction is at Label if
  t4!t5
• beq t4,t5,Label Next instruction is at Label if
  t4t5
• Format
• 16-bit address is relative to Program Counter
  (offset)
• most branches are local (principle of locality)
• offset is sign-extended before added to PC
• Important
• offset is relative to address of following
  instruction (PC4)
• offset uses word addressing (must be mult. by 4
  before added to PC4). Why? Study example on page
  149/150 carefully.

24
Addresses in Jumps

• Instruction
• j Label Next instruction is at Label
• New format
• Jump instructions use four high order bits of PC
• Address boundaries of 256 MB
• Also specify word addresses

25
Control Flow

• We have beq, bne, what about Branch-if-less-than
  ?
• New instruction if (s1 lt s2)
  t0 1
• slt t0, s1, s2 else t0
  0
• Can use this instruction to build blt s1, s2,
  Label. How?
• blt, bgt, ble, are all accepted by assembler
  (pseudo-instructions) and translated to real MIPS
  instructions
• Assembler needs a register (at) to do this,
  there are policy of use conventions for registers

26
MIPS Register Conventions
27
Constants

• Small constants are used quite frequently (50 of
  operands), e.g., A A 5 B B
  1 C C - 18
• Possible solutions
• put 'typical constants' in memory and load them
• create hard-wired registers (like zero) for
  constants like one
• put constant in instruction (MIPS)
• MIPS instructions addi 29, 29, 4 slti 8,
  18, -10 andi 29, 29, 6 ori 29, 29, 4
• I-type instructions (I is for immediate)
• There is no subi instruction. Why not?

3
28
How about larger constants?

• We'd like to be able to load a 32-bit constant
  into a register
• New "load upper immediate" instruction
• Example suppose we want to load 0xaabbccdd
• lui t0, 0xaabb

• Then we must get the lower order bits right,
  i.e., ori t0, t0, 0xccdd

0xaabb
0x0000
0x0000
0xccdd
ori
0xaabb
0xccdd
29
Case/switch statement

• Case/switch statement
• can be translated to a chain of if-then-else
  statements
• worst case running time proportional to number
  of cases
• can be done faster using a jump address table
• New instruction jump register
• jr t0
• Example
• switch (k)
• case 0 f ij break
• case 1 f gh break
• case 2 f g-h break
• case 3 f i-j break

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Case/Switch statement
slt t3, s5, zero bne t3, zero,
Exit slti t3, s5, 4 beq t3,
zero, Exit add t1, s5, s5 add
t1, t1, t1 add t1, t1, t4 lw
t0, 0(t1) jr t0 L0 add s0, s3,
s4 j Exit L1 add s0, s1, s2
j Exit L2 sub s0, s1, s2 j
Exit L3 sub s0, s3, s4 Exit
Assembler code
1. test if 0 lt k lt 3 2. compute address 3.
fetch jump address and jump 4. code for all cases
Data jump table
address L0 address L1 address L2 address L3
t4
t44
t48
t412
31
Summary

• Assembly provides convenient symbolic
  representation
• much easier than writing down numbers
• Machine language is the underlying reality
• Assembly can provide 'pseudoinstructions'
• e.g., move t0, t1 exists only in assembly
• would be implemented using add t0,t1,zero
• MIPS overview
• simple instructions, all 32 bits wide
• very structured, no unnecessary baggage
• only three instruction formats

32
Active Learning

• Question taken from last years exam
• Translate the following C code to MIPS assembly.
  Assume
• base address of a is contained in a0
• max is contained in v0
• int a100, i, max
• max 0x80000000 / the smallest 32-bit int /
• for (i0 ilt100 i)
• if (ai gt max)
• max ai

33
Procedures/functions

• Extremely useful in high-level languages
  (abstraction!)
• Necessary steps
• Place parameters somewhere where the callee can
  find them
• Save return address and transfer control to
  function
• Allocate space for local variables
• Do your thing
• Place results somewhere where caller can find
  them
• Return control to point of origin

34
Procedures/functions

• MIPS register conventions
• a0 - a3 4 argument registers
• v0 - v1 2 result registers
• ra return address
• New instruction jump and link
• jal FunAddress save return address in ra
• en jump to FunAddress
• Program Counter (PC) contains address of current
  instruction, all MIPS instructions are 32 bits,
  so return address is?
• But how do we return to point of origin?

35
Compiling a leaf procedure

• void swap(int v, int k) swap add t0,a1,a1
• add t0,t0,t0
• int tmp add t0,a0,a0
• tmp vk lw t1,0(t0)
• vk vk1 lw t2,4(t0)
• vk1 tmp sw t2,0(t0)
• sw t1,4(t0)
• jr ra
• Caller
• add a0,s1,zero
• add a1,s2,zero
• jal swap

36
Stack

• Problems, problems, problems, ...
• What if a functions calls another function?
• What if a function has more than 4 arguments
• What if?
• Important data structure
• stack last-in-first-out (LIFO) queue
• 2 operations
• place something onto the stack (push)
• remove something from the stack (pop)
• In MIPS
• stack grows from high to low addresses
• stack pointer (sp) points to top of stack

37
Stack

• MIPS register conventions
• t0-t9 10 scratch registers that are not saved
  by callee
• s0-s7 8 saved registers that must be saved by
  callee

low address
Save s0 en s1
addi sp,sp,-8 lw s0,4(sp) lw s1,0(sp)
empty
sp
Restore s0 en s1
filled
sw s0,4(sp) sw s1,0(sp) addi sp,sp,8
high address
38
Compiling a non-leaf function
int square(int a) square return
aa mul v0,a0,a0 jr ra int
poly(int x) poly addi sp,sp,-8 return
square(x)x1 sw ra,4(sp) sw a0,0(sp
) jal square lw a0,0(sp) add
v0,v0,a0 addi v0,v0,1 lw ra,4(sp
) addi sp,sp,8 jr ra
39
Recursive functions
C function that computes factorial
int fact (int n) if (nlt1) return (1)
else return (nfact(n-1))
Factorial n! n (n-1)!
0! 1
40
Recursive functions
Assembly-code for fact
instruction address 1000 fact addi
sp,sp,-8 1004 sw ra,4(sp) 1008
sw a0,0(sp) 1012 slti t0,a0,1
test if nlt1 1016 beq t0,zero,L1 if
ngt1 goto L1 1020 addi v0,zero,1
return 1 1024 addi sp,sp,8 check
this! 1032 jr ra 1036 L1 addi
a0,a0,-1 1040 jal fact call
fact with (n-1) 1044 lw a0,0(sp) 1048
lw ra,4(sp) 1052 addi
sp,sp,8 1056 mul v0,a0,v0 return
nfact(n-1) 1060 jr ra
41
Recursive functions
low address
v0 1
100 addi a0,zero,3 104 jal fact 108 ....
v0 1
v0 2
sp
v0 6
filled
high address
42
Beyond numbers characters and strings

• Characters are often represented using ASCII
  (American Standard Code for Information
  Interchange). See Table 3.15, page 142
• Note value(a) - value(A) 32
• value(z) - value(Z) 32
• MIPS has load byte and store byte instructions
• lb t0,0(gp)
• sb t0,0(gp)
• A string is a sequence of characters
• In C, a string is terminated by byte 0
• aap 97,97,112,0

43
Starting a program

• Compile C program
• Assemble
• Link
• insert library code
• determine addresses of data and instruction
  labels
• relocation patch addresses
• Load into memory
• load text (code)
• load data (global data)
• initialize sp, gp
• copy parameters to the main program onto the
  stack
• jump to start-up routine
• copies parameters into ai registers
• call main

44
Starting a program
C program
compiler
Assembly program
assembler
Object program (user module)
Object programs (library)
linker
Executable
loader
Memory
45
To summarize
46
To summarize
47
MIPS addressing modes summary
48
Exercises

• Make from chapter three the following exercises
• 3.1 - 3.6
• 3.8
• 3.16 (calculate CPI for gcc only)
• 3.19, 3.20