Information Security Using the SHA1 Algorithm

1
Information Security Using the SHA-1 Algorithm

• Group Members
• Bernard Ng
• D. Eric Harrah
• Jason Koay
• Adam Miller

2
Overview

• Project Goals
• Basic Algorithm
• Virtex Implementation
• Simulation of Virtex Implementation
• hp26g Implementation
• Simulation of hp26g Implementation
• Conclusions

3
Project Goals

• Modify existing VHDL to create implementations of
  the SHA-1 algorithm on
• Xilinx Virtex 300
• hp26g
• Generate pre-layout and post-layout simulations
  of both implementations using Mentor Graphics
  ModelSim.

4
Algorithm
5
Algorithm (Initialization)

• The message digest is divided into 64 byte
  blocks.
• Message is less than 261 bytes.
• Message will be padded to be a multiple 64 bytes.
• A key of 5 constants are chosen H0-H5. They are
  4 bytes (1 word) long.

6
Algorithm (Block Processing I)

• Divide block into 16 words.
• Create words 16-79 with
  WtS1(Wt-3XOR Wt-8XOR Wt-14XOR Wt-16)
• Let AH0, BH1, CH2, DH3, EH4

7
Algorithm (Block Processing II)

• For t0 to 79 do
• TEMPS5(A)f1(B,C,D)EWtKt
• ED, DC, CS30(B), BA, ATEMP
• Let H0H0A, H1H1B, H2H2C, H3H3D, H4H4E
• Repeat on next 64 byte block

8
Virtex Implementation

• Virtex 300
• Insufficient memory
• Virtex 1000
• Has required memory elements
• Problems encountered
• Small Chips
• Long run time for Optimization
• Lack of .pkt files for most Virtex chips

9
Virtex Implementation

• Place and Route for Xilinx
• Ran into problems with the memory blocks
• PAR did not properly handle the inputs from the
  Block RAM
• PAR could not provide a connection for the input
  from the memory

10
Simulation Virtex

• Mentor Graphics ModelSim
• Because of the complexity of the design, the
  systems that ModelSim was run on did not have
  enough memory or processing capability to
  successfully simulate the design.

11
hp26g Implementation

• Synopsys Design Analyzer, using hp26g ruleset.
• Possible to implement design, but the Virtex SRAM
  component that made up the memory was missing
  from the libraries.

12
hp26g PAR and Simulation

• Due to the problems with the missing SRAM
  component, Epoch was never able to place and
  route a layout.
• Simulation of either the pre-layout or
  post-layout files was not possible because of the
  missing components

13
Conclusions

• Virtex implementation
• hp26g implementation
• If an SRAM module was created to mimic the Virtex
  SRAM, the chip probably could have been
  implemented and possibly simulated.