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Self_Biasing PLL Design

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Self_Biasing PLL Design. Peiqing zhu. VCO design. 8-stages delay cell. Simulation result ... Idc=3.6mA for every delay cell. F=2.6Ghz ... – PowerPoint PPT presentation

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Title: Self_Biasing PLL Design


1
Self_Biasing PLL Design
  • Peiqing zhu

2
VCO design
  • 8-stages delay cell

3
Simulation result
4
VCO Design(2)-4 stages delay cell
5
Simulation result_1
6
Simulation result_2
7
OPamp Design
8
Simulation result_1
9
Simulation result_2
10
Simulation result of biasing generator and
4_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F2.6Ghz
11
Simulation result of biasing generator and
8_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F1.3Ghz
12
Simulation result of biasing generator and
12_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F0.866Ghz
13
Simulation result of biasing generator and
4_stages VCO
Output swing voltage0.7v Idc0.9mA for every
delay cell. F1.345Ghz
14
Simulation result of biasing generator and
8_stages VCO
Output swing voltage0.7v Idc0.9mA for every
delay cell. F0.660Ghz Now we can update this
frequency to 1.3GHz in the new version
15
Conclusion
  • 1)VCO using 4_stages has some distortions but
    has a higher speed (up to 2.6GHz)
  • 2)VCO using 8_stages has no distortion but has a
    lower speed (up to 1.3GHz)
  • 3)VCO speed is limited by the charge or
    discharge capacitance time.

16
VCO delay cell
Parasitic capacitance
17
8_Stages VCO Schematic
18
8_Stages VCO Layout
19
8_Stages VCO Post Layout Simulation
20
Opamp_Design
21
Simulation Result
3dB bandwidth 1.67Ghz
Phase Margin 54deg
22
VCO Design-delay cell design
23
8_Stages VCO Design
24
VCO output frequency1.30GHz
25
VCO Simulation Result
26
Biasing Generator and VCO
27
Simulation Setup for the VCO
28
Simulation Result
Output frequency1.24GHz
29
VCO GAIN
30
Charge Pump Design
31
Charge Pump Design Xor gate
32
Xor Simulation Result
33
S2D Module Design
34
S2D Simulation Result_100MHz Input signal
S2D Module Simulation Result
INPUT SIGNAL
35
S2D Simulation Result_200MHz Input signal
INPUT SIGNAL
36
XOR2 Design_Version2
37
XOR2 Simulation Result
38
S2D Modulator
XOR2
39
Simulation Result For the S2D
40
Charge Pump Design_1
Ibiasing3.619mA
41
Charge Pump Simulation Result_1
When IDN pulse width is 5ns /10ns and IUP pulse
width is 1ns/10ns
42
Charge Pump Simulation Result_2
When IDN pulse width is 3ns /10ns and IUP pulse
width is 1ns/10ns
43
Charge Pump Simulation Result_3
When IDN pulse width is 1ns /10ns and IUP pulse
width is 3ns/10ns
44
Charge Pump Simulation Result_4
When IDN pulse width is 1ns /10ns and IUP pulse
width is 5ns/10ns
45
Charge Pump Simulation Result_5
When IDN pulse width is 1ns /10ns and IUP pulse
width is 1ns/10ns
46
Charge Pump Simulation Result_6
When IDN pulse width is 3ns /10ns and IUP pulse
width is 3ns/10ns
47
PFD Design
48
PFD Schematic
49
PFD Simulation Setup
50
PFD Simulation Result
When the data input frequency200MHz,and dclock
frequency190MHz
51
PFD Simulation Result
When the data input frequency190MHz,and dclock
frequency200MHz
52
PFD Simulation Result
When the data input frequency200MHz,and dclock
frequency200MHz
53
Diff2Single Converter
54
D2S Simulation Setup
55
Simulation Result_1
When the input signal frequency2GHz
56
Simulation Result_2
When the input signal frequency2.5GHz
57
Simulation Result_3
When the input signal frequency3GHz
58
D2S Schematic
59
Simulation Result_1
When the input signal frequency1.5GHz
60
Simulation Result_2
When the input signal frequency2GHz
61
Simulation Result_3
When the input signal frequency2.5GHz
62
Simulation Result_4
When the input signal frequency3GHz
63
Divided_By_20 Circuit Design
64
Divider_By_20 Schematic
65
Schematic of Divided_By_4
66
DFF in the Divider
67
Simulation Result of Divided_By_4
When input signal frequency1GHz
68
Simulation Result of Divided_By_4
When input signal frequency2GHz
69
Simulation Result of Divided_By_4
When input signal frequency3.3GHz
70
Schematic of Divided_By_5
71
Simulation Result of Divided_By_5
When input signal frequency500MHz
72
Simulation Result of Divided_By_5
When input signal frequency1GHz
73
Simulation Result of Divided_By_5
When input signal frequency2GHz
74
The Schematic of Divider_By_20
75
The Simulation of Divider_By_20
When input signal frequency1GHz
76
The Simulation of Divider_By_20
When input signal frequency1.5GHz
77
The Simulation of Divider_By_20
When input signal frequency2GHz
78
The Simulation of Divider_By_20
When input signal frequency3.3GHz
79
VCOD2S Design
80
VCOD2S Schematic
81
VCOD2S Schematic Simulation Result
When Vctrl1.2v,ie, the VCO output
frequency1.45GHz
82
VCOD2S Schematic Simulation Result
When Vctrl1.3v,ie, the VCO output
frequency1.36GHz
83
VCOD2S Schematic Simulation Result
VCO OUTPUT
D2S OUTPUT
When Vctrl1.4v,ie, the VCO output
frequency1.25GHz
84
VCOD2S Schematic Simulation Result
When Vctrl1.5v,ie, the VCO output
frequency1.15GHz
85
VCOD2S Schematic Simulation Result
When Vctrl1.6v,ie, the VCO output
frequency1.01GHz
86
VCOD2SDivider Schematic
87
VCOD2SDivider Simulation Result
When Vctrl1.2v,ie, the VCO output
frequency1.40GHz
88
VCOD2SDivider Simulation Result
When Vctrl1.3v,ie, the VCO output
frequency1.31GHz
89
VCOD2SDivider Simulation Result
When Vctrl1.4v,ie, the VCO output
frequency1.22GHz
90
VCOD2SDivider Simulation Result
When Vctrl1.5v,ie, the VCO output
frequency1.11GHz
91
VCOD2SDivider Simulation Result
When Vctrl1.6v,ie, the VCO output
frequency0.989GHz
92
PFDS2D Schematic
93
PFDS2D Schematic Simulation Results
When Data signal leads the Clk signal, the UP
signal goes to high PW of data signal10ns,
and PW of CLK12.5ns, PW Pulse Width
94
PFDS2D Schematic Simulation Results
When Data signal frequency is equal to the Clk
signal, the UP and DOWN signal goes to high _at_
same time. PW of data signal12.5ns, and PW of
CLK12.5ns
95
PFDS2D Schematic Simulation Results
When Data signal frequency lags to the Clk
signal, the DOWN signal goes to high PW of
data signal12.5ns, and PW of CLK10ns
96
PFDS2D Schematic Simulation Results
When Data signal leads the Clk signal, the UP
signal goes to high PW of data signal4.8ns,
and PW of CLK5ns, PW Pulse Width
97
PFDS2D Schematic Simulation Results
When Data signal frequency is equal to the Clk
signal, the UP and DOWN signal goes to high _at_
same time. PW of data signal5ns, and PW of
CLK5ns
98
PFDS2D Schematic Simulation Results
When Data signal frequency lags to the Clk
signal, the DOWN signal goes to high PW of data
signal5ns, and PW of CLK4.8ns
99
Symmetric Resistor
Requvalent170ohm
100
Loop Filter Design
101
Start Up Circuit
102
Start Up Circuit Simulation Result
103
1.25GHz Self_Biasing PLL Schematic
104
Self_Biasing PLL Simulation Result
105
Self_Biasing PLL Simulation Result (Zoom In)
VCO DIFF OUTPUT
VCO Single End OUTPUT
DCLOCK
Vref Signal
Vcontrol Voltage
Lock time2.3us
106
1.25GHz Self_Biasing PLL Schematic(modified_1)
107
Self_Biasing PLL Simulation Result
108
Self_Biasing PLL Simulation Result (Zoom In)
109
1.25GHz Self_Biasing PLL Schematic(modified_2)
110
Self_Biasing PLL Simulation Result
111
Self_Biasing PLL Simulation Result (Zoom In)
112
1.25GHz Self_Biasing PLL Schematic(modified_3)
113
Self_Biasing PLL Simulation Result (typical)
114
Self_Biasing PLL Simulation Result (Zoom In)
115
Self_Biasing PLL Simulation Result (SS)
116
Self_Biasing PLL Simulation Result (SS
Corner,Zoom In)
117
Self_Biasing PLL Simulation Result (FS)
118
Self_Biasing PLL Simulation Result (FS
Corner,Zoom In)
119
Self_Biasing PLL Simulation Result (SF
Corner,Zoom In)
120
Self_Biasing PLL Simulation Result (SF
Corner,Zoom In)
121
Self_Biasing PLL Simulation Result (FF
Corner,Zoom In)
122
Self_Biasing PLL Simulation Result (FF
Corner,Zoom In)
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