Design of HighPerformance Microprocessor Circuits

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Design of High-Performance Microprocessor Circuits
Chapter 5 SOI Technology and Circuits

• Professor Wayne Burleson
• Department of Electrical and Computer Engineering
• University of Massachusetts at Amherst
• burleson_at_ecs.umass.edu
• http//www.ecs.umass.edu/ece/vspgroup/burleson.htm
  l

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Acknowledgement and Bibliography

• Design of High-Performance Microprocessor
  Circuits
• IEEE Press, Piscataway, NJ, 2000. ISBN
  0-7803-6001-X
• Chapter 5 SOI Technologies and Circuits
• Ghavam G. Shahidi, IBM
• Fari Assaderaghi, IBM
• Dimitri Antoniadis, Massachusetts Institute of
  Technology
• Editors
• Anantha Chandrakasan, Massachusetts Institute of
  Technology, Cambridge, MA
• William J. Bowhill, Compaq Computer Corporation,
  Shrewbury, MA
• Frank Fox, Rambus Inc., Mountain View, CA

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Introduction
Initiative CMOS scaling in conventional
ULSI system approaches its limit for

improving system performance. SOI can
improve CMOS performance.
Challenges 1. Material quality. 2. SOI
device design. 3. Bulk CMOS scaling and
resulting performance gain per generation. 4.
The lack of demonstration of a mainstream complex
SOI based application. 5. The restriction of
SOI nFETs burn-in voltage to low values.
Progresses and new circuit behaviors 1. SOI
material quality has improved significantly with
better understanding of SOI defects, their
characterization and impacts on the devices and
circuits. 2. Partially depleted(PD) SOI device
design and the corresponding floating-body,
self-heating effects.
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Device Design Considerations for PD SOI/FD SOI
Main feature of MOS in SOI Devices local
substrate is electrically floating and therefore
its voltage VBS is not fixed.
Static-steady-state condition VBS is determined
by the balance of DC currents through the two
back-to-back diodes and impact ionization near
the drain. Impact ionization is the creation of
hole-electron pairs caused by channel carriers
traveling through high field region near drain in
saturation. Normal device operation Minority
carriers and channel carriers are swept to the
drain, causing no effect. Majority carriers are
swept to the substrate causing substrate current
Iii. Dynamic switching VBS depends on the
previous electrical switching history of the
device, as well as on the instantaneous node
voltages through the capacitive network.
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Kink Effect
Kink effect Under static conditions, the
modulation of VT, can be found in the output I-V
characteristic as the increase of the output
conductance of device near VDS1V. However,
dynamic VT variation can significant improve the
performance of digital circuits in PD SOI.
Reason Impact-ionization-induced increases VBS
with increasing VDS, and reducing of VT. When VDS
becomes large enough, impact ionization current
flows to the undepleted body increasing the body
charge and therefore VBS. Solution Use FD SOI
devices. SOI thickness is less than the minimum
channel depletion width. Body charge is fixed and
any impact ionization charges flowing into the
depleted body are readily swept to the source due
to the much reduced potential barrier.
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Short-Channel Effects and the Advantages of PD SOI
Short-channel effects(SCE) The roll-off of VT
with the decrease of channel length. As the film
thickness is reduced, the VT roll-off does
improve by the reduction in junction depth. For a
given channel length, FD SOI devices exhibit
increased SCE relative to PD SOI unless the
silicon film thickness becomes much less than the
depletion depth.
Advantages of PD SOI Less SCE, easier to
manufacture because of its large thickness,
easily achieved high VT, simple implementation of
multiple-VT. Disadvantages of PD SOI
History-dependence of propagation delay,
floating-body effects.
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SOI Device Self-Heating
Self-Heating The reduction of thermal
conductance of the substrate, which results in
the increase of the device temperature, with the
corresponding reduction in current and possible
impact on reliability. Manifestation Negative
differential output resistance. Typical
parameters Conventional chip, 1-D heat
resistivity 20 mK/(W/CM2). SOI with buried oxide
thickness of 200 nm, 1-D heat resistivity
21.3mk/(W/CM2), normalized 3-D heat resistivity
60-100 ?mK/mW. Temperature rise 2-3k in most
SOI devices,10-15K in terminated output drivers,
due to the domination of 1-D heat flow and the
drain voltage transient(usually not full swing)
power consumption.
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VT Variation Due to Floating Body (1)
The body voltage is determined by the leakage
current of the p-n diodes and the impact
ionization currents(a), and by the capacitive
coupling to device terminals during
switching(b). The response time of the leakage
and impact ionization currents is slow while the
response time of capacitive coupling is fast. In
PD SOI, VBS0 (in nFETs, opposite in pFETs) in
most cases. Body contact device structures can be
used to avoid the floating-body effects.
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VT Variation Due to Floating Body (2)
DC mode Obvious kink effect, particularly at low
VGS values. Body-tied-VBS0 mode No kink effect,
negative output conductance at high VGS values
due to the self-heating effect. Transient mode
Because of the ns-rise-time VGS pulses from 0V to
the desired measurement value, the instantaneous
value of VBS is determined by the capacitive
coupling and by the initial conduction of VBS
that in turn is determined by the steady state
for VGS0 and the VDS value of each measurement
point.
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VT Variation Due to Floating Body (3)
Simulated VBS and VDS voltages for a rising VGS
transient in a CMOS inverter. The propagation
delay is reduced as the benefit from the
transient rise in VBS.
The increase in current is due to the capacitive
coupling and the elimination of self-heating
effect.
PD-SOI MOSFETs have larger drain-induced barrier
lowering (DIBL) and lower saturation VT than
bulk CMOS counterparts due to the increase of
floating-body VBS in the forward direction with
increasing VDS. With proper device design, at
the elevated temperature of operation in
high-performance MPUs, the difference is
negligible.
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PD-SOI CMOS Digital Circuits

• Three primary causes of performance gain of SOI
  over bulk CMOS
• Area and exterior periphery junction capacitance
  is nearly absent in SOI.
• MOS reverse-body-voltage effect is absent in SOI,
  because the body-source is typically forward
  bias.
• SOI on current during the switching transient
  is higher than that in bulk CMOS due to the
  forward VBS.

Circuit
(tBULK-tSOI)/tBULK CPU1
L2 Directory Access time
29.8 CPU2 (Gate dominated)
27.1 CPU2 (Wire
dominated)
20.9 CPU3 (Gate dominated)
30.4 CPU3 (Wire
dominated)
19.6
Comparison of critical paths in microprocessors
based on 0.22 µm CMOS-SOI.
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History Dependence of Propagation Delay (1)
History dependence Uncertainty or variation in
delay through a gate. Cause Variability of VBS
and the subsequent variation in VT.
The delay is shorter when the driving pulse
period is slower. The delay increases as the VDD
voltage decreases because the proportion of
floating-body-dependent VT variation increases.
During switching, VBS of SOI devices undergoes
considerable variation. VBS is in the forward
switching direction leading to reduced VT and
therefore increased switching current. This
pre-switching VBS for the first transition
(away-from initial state) is determined by the
static steady-state balance of DC currents. For
the second transition (return-to initial state)
it is determined by the capacitive network.
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History Dependence of Propagation Delay (2)
Due to the small diode leakage and impact
ionization currents as means of changing the body
charge, it takes a long time and a large number
of cycles for body net charge to change from
initial static- to switching-steady-state. The
slow change of pre-switch VBS will result in that
the inverter rise times change slowly over time
and are different in steady state from what they
are during the first switch from static state.
The maximum variation in delay observed
experimentally for a number of gates between
static- and switching-steady-state is between 3
and 7, which is generally smaller than the other
source of uncertainty in a chip.
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Pass-Gate Transient Leakage
In SOI, if the source and drain are both high for
a relative long interval, the body charges up to
VDD through diode leakage. When the gate is off,
the channel accumulates holes. If the source is
pulled low, a transient forward VBS appears
across the source-body diode, which can turn on
the parasitic source-body-drain npn bipolar
transistor of the nFET and give rise to a pulse
of current in the device. Solution (1) Minimize
the BJT gain by proper source-body diode doping
design that makes carrier injection into the
source more efficient. (2) Minimize the initial
transient VBS by scaling down VDD with advancing
CMOS generation or by proper balancing of the
source-body junction versus gate-body capacitance
for minimum-size devices.

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Hysteretic Gate Delay
Circuit Issues in PD-SOI CMOS Hysteretic
gate-delay, pass-gate transient leakage, VT
mismatch, reduced noise margin in SOI, and
circuit operation at screening(burn-in)
voltages. Sources of Uncertainty History effect,
poly-width variation, VDD and temperature
variations, noise, switching patterns, device
degradation. Uncertainty Management Margins in
the critical timings.
SOI history dependence is in the same order of
magnitude as other uncertainty in typical bulk
CMOS design, the margins in the timing rules
should be slightly increased. The delay
variations of most circuits can be bound by
initializing the body to high (fastest case) or
low (slowest case). Use fastest timing rules for
fast path and use slowest body setting for
performance sizing. Also by initializing the chip
at different initial chip logic conditions prior
to running the cycle-limiting path and measuring
the resulting variations in the cycle time, the
impact of history effect can be estimated. On the
processor level, this effect is only 2, less
than that of the worst case in a number of logic
gates.
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Transient Pass-Gate Leakage Effect on Circuits (1)
Two classes of circuits that are
susceptible to transient pass-gate leakage which
leads to parasitic current and causes circuit
failure even though the gate is off. (1) Nodes
with no keeper device, such as DRAM. (2) Wide
NORs, such as SRAMs.
In the wide NOR in dynamic circuits, if VD and VS
across all of the devices are high for a long
time, they will accumulate. If device C is turned
on, a pulse of current will be passed through
device Ai. If accumulated channel width of Ai is
large enough, the dynamic node can be
discharged. Solution Increase the size of the
keeper, limit the cumulative width of NOR
function ,eliminate the charge-sharing pFET,
discharge the common source of Ai periodically.
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Transient Pass-Gate Leakage Effect on Circuits (2)
In SRAMs, pass-gate leakage through a large
number of pass-gate-configured access transistors
on the bit line can impact the SRAM timing,
depending on the pattern held in the SRAM
cell. If all cells on a bit line(BL) hold 1 for
enough time for the access transistors to
accumulate, then writing 0 to a cell on the bit
line would cause all other cells to inject their
transient pass-gate leakage current on the BL.
The excess current acts as extra load on the
write amplifier, Thus, write time would be longer
than the case where all the cells were kept 0.
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Transient Pass-Gate Leakage Effect on Circuits (3)
If all the cells hold 1 except for one cell
that holds 0, then when reading the 0 all
other cells would discharge and increase the time
that differential voltage between BL and BL-bar
needs to develop. Minimization of transient
pass-gate leakage Limit the number of cells in
a bit line, precharge the BL to less than full
VDD, use super-bit line architectures, increase
the size of write drivers, or simply ignore the
problem, if it is limited to high-voltage stress
corners.
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Reduced Noise Margin and VT Mismatch
Noise Analysis FET SOI body can charge up to
relative large forward voltage, which leads to
the reduction of VT. Smaller VT will make
circuits susceptible to noise. Elimination of the
well-substrate capacitance on SOI and the reduced
junction capacitance decreases the fixed cap on
the nodes and makes them more susceptible to
interconnect coupling than bulk CMOS.
VT Mismatch
VBS is dependent on the switching history. When
sense amplifier in SRAM is repeatedly reading the
same pattern, differential in VBS and VT
develops. Solution will be body contacts on the
input devices of the sense amplifier
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SOI for Low Power
For a given CMOS generation, SOI has higher
performance than comparable bulk technology. This
performance headroom allows for operation at
lower voltage and much lower power. VBS is in the
forward direction in most switching cases.
Forward VBS dynamically lowers VT, and lower
VT is valuable at low voltage operation where
performance and functionality is proportional to
VDD-VT.
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Conclusion
PD-SOI CMOS technology has considerable advantage
over FD-SOI technology in terms of design point
and manufacturability. The sources of SOI
performance advantages enable SOI CMOS to achieve
20-35 performance advantage over bulk CMOS. The
floating-body topology has effects such as
history dependence of gate delay and the
transient. The effects can impact circuit
functionality, however circuits can be designed
around them and their effects are manageable.