Optical Ethernet Design

1
Optical Ethernet Design

• Receiver Group G1
• David Gewertz
• Ryan Baldwin
• Geoffrey Sizemore
• Presented February 14, 2002

2
Outline

• Understanding of previous team progress
• removal, redesign, debug
• Maxim Evalution Kit
• understand chip functionality and future
  applications
• Redesign transeiver for Gigabit Ethernet
• replacement, improvement
• Testing and verification
• BER, compatibility, signal quality

3
Previous Teams Progress

• Design Team Objectives
• Separation of optical transceiver from Intel card
• Redesign and fabrication of new board containing
  optical functionality
• Reintegration of board with Intel setup
• Verification to meet optical ethernet
  specifications
• Use of evaluation kits in further design efforts

4
Pitfalls and Resolutions
5
Final Circuit Diagram (Fall 2001)
6
Maxim Evaluation Kits

• MAX3266 Evaluation Board Diagram

Photodiode emulation circuit replaced by
photodetector
7
Maxim Evaluation Kits

• Circuit Modifications to Minimize Current Loss
• Replacing series resistors and adding a 67-Ohm
  resistor in parallel

8
MAX3266 Board Functionality

• Photodiode emulation
• inexpensively mimic the output of a photodetector
  for chip feature testing
• Transimpedance Amplifier (TIA) on chip
• converts current to voltage
• converts single-ended input to differential
  output
• 1 mA p-p input 250 mV p-p output
• 10 micro-A p-p input 2.5 mV p-p output

9
Maxim Evaluation Kits

• MAX3264 Evaluation Board Diagram

10
MAX3264 Board Functionality

• Proper termination impedance and series
  capacitors to maintain voltage regularity
• Buffer on chip
• maintains integrity of output from TIA
• Limiting Amplifier on chip
• provides 55 dB gain with 1.2 Volt max
• low jitter enables higher speeds
• RMS Power Detection

11
Testing and Verification

• BERT
• Tektronix GTS 1250 (1250 Mb/s)
• desired BER 10-12 or 1 error every terabit
• Example - For a 4 MB MP3, that would be one bit
  error for every 31,000 songs transferred
• Tektronix CSA 7xxx Scope
• accurately measures and records Gb eye diagrams
• uses specially designed Communications Signal
  Analyzer software

12
Design

• Single PCB with both chips
• Interface with other design groups (OE, TX)
• Interference-free implementation of a single
  power source to drive all active components

13
Conclusions

• Gb Ethernet technology has been researched and
  understood
• Fall 2001 group projects have been studied for
  increased understanding and legacy development
• Maxim data sheets have been analyzed
• Initial research has been completed

14
Conclusions

• Next Steps
• Get previous teams testbed up and functional
• Connect and test Maxim boards
• Understand development of a receiver module and
  implement it using our own design