Overview of LDRD Read Out Card ROC

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Overview of LDRD Read Out Card (ROC)

• Anuj K. Purwar
• August 29, 2006

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ROC the need

• Sits in the IR near FPIX/sensors.
• Read data from FPIX, strip off sync word and
  send it off to FEM by fiber.
• Implement slow controls for FPIX e.g. channel
  masks.
• Interface with calibration system.

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ROC Specifications

• To handle 8-chip module gt 36 LVDS channels.
• Ability to handle 4 lines/FPIX gt 555 to 680
  Mbps per FPIX.
• Radiation tolerance 100 kRads and 1.4 x 1012
  neutrons/cm2.

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Block diagram for Read Out Card
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Calibration System (by Pat)
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Data Path through ROC

• FPIX Core CLK 3 x BCO gt DCLK 180 MHz (DDR
  equivalent).
• 10 hits in Central AuAu gt 3.3 BCO CLK latency
  in read out.
• ROC to fiber latency 0.6 BCO CLK.

FPIX DCLK 180 MHz
ROC Combines n-FPIX
Serdes/Fiber
Fiber
28-bit word
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Bandwidth requirements

• DCLK 180 MHz gt 680 Mbps/FPIX.
• ROC needs to handle N x 680 Mbps.
• If fiber speed 3 Gbps, then 4 FPIX/fiber.
• If greater latency permitted, then 8 FPIX/fiber
  (hits stored on FIFO).

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Actel ProASIC3 Test Board

• ProASIC3 A3P250 chip.
• 34 LVDS I/O.
• Flash based config memory.
• All FPGA pins available.
• FIFO speed 350 MHz (240 MHz required for 8 chip
  module).

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Current status

• Two designs
• 1 FPIX design (implements DDR and basic download
  capability including FFR, Alines etc.
• 4 FPIX design implements only readout (using
  multiplexer/FIFO running at 120 MHz).
• Working on pre-prototype PCB with appropriate
  connectors and LVDS terminations to test design 1
  and 2.

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To Do

• Which fiber/serializer combination?
• How to implement slow controls (including GTM)
  over 1 fiber?
• Interface with calibration system.
• Prototype board design with bigger ProASIC3,
  EPROM for FPIX download info and Serdes/Fiber
  combo for 8 chip module.