Closed Loop Combustion Control FPGA for high bandwidth control

1
Closed Loop Combustion Control FPGA for high
bandwidth control

• Carl Wilhelmsson

2
Overview

• Hardware in use
• Description of current simulink layout
• Live demonstration of current design
• System frequencies
• Brief outlook describing future possibilities and
  interests
• Date of publication

3
Field Programmable Gate Array (FPGA)
4
Inside the FPGA
Configurable Logic Block (CLB)
Field Programmable Gate Array (FPGA)
Programmable Switch Matrices (PSM)
Input Output Block (IOB)
5
FPGA // Processor

• FPGA propagates signals through digital logics,
  allowing true parallel operation // Processor
  execute one instruction at a time.
• FPGA internal connection scheme are described by
  a bit mask, no instructions are run on the
  chip // Processor execute instructions
• Nature of FPGA allows strict time deadlines on
  the results // Processor need advanced real-time
  handling

6
Hardware

• Xilinx Virtex 4 FPGA, 24200 logic cells 168Kb
  ram, 100MHz clock
• Memec Virtex4 LC prototype board (www.memec.com)
• Expansion header for prototype analog design
• Ethernet, RS232, 2x20 LDC display etc
• Memec P160 Analog expansion card
• Dual 53 MSPS 12 bit, AD converters
• Dual 165 MSPS 12 bit, DA converters
• System cost SEK6900, 100.000, 895
  (development software)

7
Methods to configure FPGA

• Base method are a Hardware Description Language
  HDL
• Different graphical programming environments do
  exist, Xilinx ISE, System Generator DSP
  (interface to Simulink, Matlab), NI Labview
• Graphical tools generate intermediate HDL code
• A connection list is generated from the HDL
  code in a complex optimization and routing
  process
• Connection list is loaded on the FPGA, signals
  is propagated through the FPGA as described

8
Current Simulink implemented HR
9
Setup schematics
Simulated engine
Oscilloscope
Signal conditioning
10
System frequencies

• FPGA clock 100 MHz, up to 500MHz possible!
• AD converter clock 50 MHz
• Kistler pressure transducer natural frequency 45
  kHz
• Kistler charge amplifier frequency range 0-200
  kHz
• Engine CAD counts _at_ 1200, 7.2 kHz, (_at_ 24000,
  144kHz)

11
Time relationships

• 50 MHz throughput (AD converter slowing down) gt
  2 complete HR analysis / CAD _at_ 1200 rpm
• Current FPGA HR algorithm introduce a delay of
  30 clock cycles gt 300 ns delay
• Engine _at_ 1200rpm moves 0.00216 CAD within 300ns,
  (0.0432 CAD _at_ 24000rpm)
• HR latency of 1000 clock cycles still finishes
  within 0.072 CAD _at_ 1200 rpm

12
Multiple injection strategies/control

• SAE 2003-01-0745, HCCI Combustion in DI Diesel
  Engine, Hasegawa, Yanagihara
• Towards Cleaner Diesel Engines, Symposium 2-3
  June 2005, Lund Sweden, Combustion Phasing and
  Emission Control by using Multiple Injections on
  a Heavy-Duty Diesel Engine, Husberg, Gjirja,
  Denbratt, Engström

13
Application of FPGA on controls

• Asynchronous as it happens engine observers
• Gas composition estimation
• Pollutants formation
• Early HR development
• HR shaping
• Gas composition compensation
• Intelligent multiple injection strategies
• In cycle and between cycle, injection feedback
  strategies

14
Publication of HR results

• Abstract sent to FISITA World Automotive
  Congress, 22-27 October 2006, Yokohama, Japan
• Final date 31 May 2006
• Publication plan ok?

15
Summary

• The use of an FPGA in the control-loop introduces
  completely new possibilities especially in
  combination with high speed injectors
• It is possible to finish the analysis of a new
  pressure sample before the engine has moved 0.5
  CAD at any engine speed
• Total pricing of an FPGA development system is
  very low
• Gives the possibility to implement advanced
  observers running along with the engine