Challenges in the Area of High Performance Nanoscale Circuits PowerPoint PPT Presentation

presentation player overlay
1 / 33
About This Presentation
Transcript and Presenter's Notes

Title: Challenges in the Area of High Performance Nanoscale Circuits


1
Challenges in the Area of High Performance
Nanoscale Circuits
  • Prof. Yehea Ismail

2
The First Computer
3
ENIAC - The first electronic computer (1946)
4
The Transistor Revolution
First transistor Bell Labs, 1948
5
The First Integrated Circuits
Bipolar logic 1960s
ECL 3-input Gate Motorola 1966
6
Intel 4004 Micro-Processor
1971 1000 transistors 1 MHz operation
7
Intel Pentium (IV) microprocessor
8
Moores Law
  • In 1965, Gordon Moore noted that the number of
    transistors on a chip doubled every 18 to 24
    months.
  • He made a prediction that semiconductor
    technology will double its effectiveness every 18
    months

9
Moores Law
Electronics, April 19, 1965.
10
Evolution in Complexity
11
Transistor Counts
1 Billion Transistors
K
1,000,000
100,000
Pentium III
10,000
Pentium II
Pentium Pro
1,000
Pentium
i486
i386
100
80286
8086
10
Source Intel
1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
Courtesy, Intel
12
Moores law in Microprocessors
1000
2X growth in 1.96 years!
100
10
P6
Pentium proc
Transistors (MT)
486
1
386
286
0.1
8086
Transistors on Lead Microprocessors double every
2 years
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Courtesy, Intel
13
Die Size Growth
100
P6
Pentium proc
486
Die size (mm)
10
386
286
8080
8086
7 growth per year
8085
8008
2X growth in 10 years
4004
1
1970
1980
1990
2000
2010
Year
Die size grows by 14 to satisfy Moores Law
Courtesy, Intel
14
Frequency
10000
Doubles every2 years
1000
P6
100
Pentium proc
Frequency (Mhz)
486
386
10
8085
286
8086
8080
1
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2
years
Courtesy, Intel
15
Power Dissipation
100
P6
Pentium proc
10
486
286
8086
Power (Watts)
386
8085
1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
16
Power is a major problem
100000
18KW
5KW
10000
1.5KW
500W
1000
Pentium proc
Power (Watts)
100
286
486
8086
10
386
8085
8080
8008
1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
17
Power density
10000
1000
Power Density (W/cm2)
100
8086
10
4004
P6
8008
Pentium proc
8085
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low
temp
Courtesy, Intel
18
Not Only Microprocessors
CellPhone
Digital Cellular Market (Phones Shipped)
(data from Texas Instruments)
19
Challenges in Digital Design
µ DSM
µ 1/DSM
Macroscopic Issues Time-to-Market
Millions of Gates High-Level Abstractions
Reuse IP Portability Predictability
etc. and Theres a Lot of Them!
  • Microscopic Problems
  • Ultra-high speed design
  • Interconnect
  • Noise, Crosstalk
  • Reliability, Manufacturability
  • Power Dissipation
  • Clock distribution.
  • Everything Looks a Little Different

?
20
Productivity Trends
10,000,000
100,000,000
Logic Tr./Chip
1,000,000
10,000,000
Tr./Staff Month.
100,000
1,000,000
58/Yr. compounded
Complexity
10,000
100,000
Productivity (K) Trans./Staff - Mo.
Complexity growth rate
1,000
10,000
x
x
100
1,000
21/Yr. compound
x
x
x
x
x
Productivity growth rate
x
10
100
1
10
Source Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
21
Effort to Maintain Moores Law
Man Hour
10,000
Pentium III
1000
Pentium II
Pentium Pro
Pentium
i486
i386
100
80286
8086
1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
22
Technology Trends
22
  • Higher operating frequencies
  • Aggressive interconnect scaling and demands on
    bandwidth
  • New devices (SOI, SiGe, )
  • Lower supply and noise margins
  • Increasing density and complexity
  • 3-D and many core technologies
  • More integration of heterogeneous technologies

?
Changing Models and New Problems and Challenges
23
Physical Level Problems in High Speed Integrated
Circuits
  • Some of the physical level new issues are
  • increased coupling noise
  • harder requirements on clock distribution
    networks and power distribution networks
  • skin and proximity effects, magnetic and
    inductance effects
  • wide bus design and data communication bottle
    necks,
  • reliability issues
  • increased leakage power
  • increased temperatures and thermal effects
  • increased variations Statistical and corner
    methods

24
Potential and Nature of Research
  • The research in these emerging physical level
    phenomena has by nature the attributes of being
  • new
  • important to industry
  • require significant theoretical background and
    analysis
  • In addition, this research is by nature
    interdisciplinary requiring knowledge about
  • circuits
  • technology and fabrication
  • electromagnetism
  • heat transfer and thermodynamics
  • physics, mathematics
  • CAD tools
  • algorithms
  • simulation techniques

25
Research Strategy
  • The explosive growth in complexity and speed of
    integrated circuits has led to issues and
    challenges in the design and analysis of high
    performance integrated circuits that previous
    generations did not exhibit.
  • Most of these issues are at the physical levels.
  • These issues are expected only to increase in
    importance in future generations of integrated
    circuits since frequencies and device densities
    will only increase.

26
Why Scaling?
  • Technology shrinks by 0.7/generation
  • With every generation can integrate 2x more
    functions per chip chip cost does not increase
    significantly
  • Cost of a function decreases by 2x
  • But
  • How to design chips with more and more functions?
  • Design engineering population does not double
    every two years
  • Hence, a need for more efficient design methods
  • Exploit different levels of abstraction

27
Cost of Integrated Circuits
  • NRE (non-recurrent engineering) costs
  • design time and effort, mask generation
  • one-time cost factor
  • Recurrent costs
  • silicon processing, packaging, test
  • proportional to volume
  • proportional to chip area

28
NRE Cost is Increasing
29
Die Cost
  • Single die

Wafer
Going up to 12 (30cm)
From http//www.amd.com
30
Cost per Transistor
cost -per-transistor
1
Fabrication capital cost per transistor (Moores
law)
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
31
Yield
32
Defects
a is approximately 3
33
Some Examples (1994)
Write a Comment
User Comments (0)
About PowerShow.com