CS 140 Lecture 18 Sequential Modules: Serial Adders, Multipliers

1
CS 140 Lecture 18Sequential Modules Serial
Adders, Multipliers

• Professor CK Cheng
• CSE Dept.
• UC San Diego

2
Overview

• Introduction
• Serial Adder
• Multiplication
• Conclusion

3
Sequential Modules Introduction

• Slice operation bitwise
• Perform process in a series of time
• Ad Cheaper hardware, Fit for FPGA architecture,
  Pipelining for excellent throughput
• Dis Longer latency

4
Serial Adder Perform serial bit-addition
At time i, read ai and bi. Produce si and
ci1 Internal state stores ci. Carry bit c0 is
set as cin
a0 b0
a3 b3
cin
Serial Adder
a b
ai
sum
si
bi
cout
s0
s3
5
Serial Adder using D F-F
Feed ai and bi and generate si at time i. Where
is ci and ci1?
6
Serial Adder using a D Flip-Flop
id ai bi ci ci1 si
0 0 0 0 0 0
1 0 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 1 0
6 1 1 0 1 0
7 1 1 1 1 1
Dci1 Qci
7
Serial Adder using a D Flip-Flop Logic Diagram
8
Serial Adder using an SR Flip-FlopExcitation
Table
id ai bi ci (Q) ci1 S R
0 0 0 0 0 0 -
1 0 0 1 0 0 1
2 0 1 0 0 0 -
3 0 1 1 1 - 0
4 1 0 0 0 0 -
5 1 0 1 1 - 0
6 1 1 0 1 1 0
7 1 1 1 1 - 0
SR generate ci1 Qci
9
Excitation Table of SR Flip-Flop
State table
S
bi
SR
inputs
0 0 1 0
PS
00 01 10 11
0 0 0 1 - 1 1 0 1 -
0 - - -
ci
ai
Q(t1)
R
Excitation table
bi
Q(t1)
NS
PS
0 1
- - 0 -
0 1
0 - 1 0 0 1 - 0
Q(t)
ci
1 0 0 0
ai
10
Serial Adder using an SR Flip-Flop Logic Diagram
S aibi R aibi
ai
si
bi
ai
Q Q
ci
S R
bi
Clk
11
Multiplication using Serial Addition
For mAxB, set m(0)0 At time i, perform
m(i1)m(i)Abi2i
12
Conclusion

• Exploration of silicon area and time domain
  design space
• Utilization of FPGA architecture
• Metrics of Cost, Speed, and Power