A Reactive Radio Architecture for PicoRadio Sensor Networks

1
A Reactive Radio Architecture for PicoRadio
Sensor Networks

• PicoRadioRF
• Nathan Pletcher, Brian Otis, Yuen-Hui Chee,
  Richard Lu, Jan Rabaey

2
Outline

• PicoRadioRF group background
• Group status update
• Reactive radio
• Upcoming research

3
PicoRadioRF Project Overview
Agilent Thin Film Bulk Acoustic Resonator
(FBAR) R. Ruby M. Frank
Wireless Sensor Node Requirements

• Extremely low power consumption
• High level of integration
• Agile transceiver (fast turn on/off)

Transceiver Characteristics

• Low data rate
• Short distance communication
• Emerging technologies (RF-MEMS)
• IMT project, Agilent

100mm
4
Group Members

• Brian Otis (architectures, receiver, RF
  oscillator)
• Yuen-Hui Chee (transmitter, PA)
• Nathan Pletcher (reactive radio)
• Richard Lu, graduated (low power LNA)
• Simone Gambini, visiting student (low power
  reference circuits)

5
Project History
Prototype chip in fab
Smorgasboard transceiver
Analog BB Prototyping
FBAR-based low power oscillator
Dec 01
Dec 02
May 03
Jan 04
Sep 02
Feb 03
Dec 03
TX chain / RX test components
Transmit Beacon
2-Channel Prototype Transceiver
B. Otis
6
Prototype PicoRadio Receiver

• Simple
• Full integration possible
• Scalable to multiple channels
• No LOs, mixers, oscillators
• Two 40kb/s channels
• Flexible OOK or FSK
• Fast turn-on time (no PLLs)

B. Otis
7
Baseband Buffers
Vdd
Vdd

• VTH-reference provides moderate supply
  independence
• Each reference biases two buffers
• Total power consumption 90µW

25µA
8kO
Vout
pad
BB in
Vin
M1
M2
Vref
10kO
Ibias (50µA)
50µA
To Ref buffer

• Designed to drive 20pF instrumentation load
• BW gt 1MHz, unity-gain stable, Aopenloop 23.4
• Power consumption 60µW per buffer

8
Buffer Startup Performance
BB buffer
Vdd
Startup time 2µs
Vout
Iref
Vref
Ref buffer
9
Prototype PicoRadio Transmitter
FBAR oscillator
Power amplifier
Baseband data
50? antenna

• Transmitter Characteristics
• Directly modulated transmitter
• Output power 0dBm (1mW)
• Low data rate (10-40 kbps)
• Narrowband system (center frequency 1.9GHz)

10
Complete 2-Channel Transceiver
(Dec 2003)
PA Test
TX1

• 0.13µm ST CMOS
• Channel selection provided by FBAR resonators
• Total die area (4x4)mm2
• Transceiver area 8mm2

LNA Test
4mm
CH1
Diff Osc
Receiver
Passive Test Structures
Env Det Test
CH2
RF Amp Test
TX2
11
Receiver Results
Vbb
Vdd
100ms/div

• -78dBm sensitivity (12dB SNR)
• 10ms turn-on time
• 3mA from 1.2V supply

B. Otis
12
Transmitter Efficiency
Maximum Efficiency 16.5 (LF) 14.7 (HF)
Maximum Output Power ? 1.9mW
Y.H. Chee
13
Performance Summary
14
Reactive Radio Overview
Main Radio
High data rate out
Wakeup signal
Carrier Sense Ckt

• Reactive radio detects broadcast wakeup signal
  and activates main radio for data transmission
• Conserves power by only turning on main
  transceiver when it is needed
• High cost for false positive wakeups
• Carrier sense receiver

15
Reactive Radio Motivation

• Tx node beacons while the Rx node periodically
  monitors the channel
• Rx channel monitoring power is significant

• Tx node beacons when it wants to transmit
• Rx node monitors the channel continuously with
  low power receiver
• Bottom Line Reactive radio must consume lt100µW
  to save power over beaconing

En-Yi Lin
16
Architecture Options
How can we build a 50µW, GHz-range carrier sense
receiver?
Next step ? Power-optimized RF oscillator
17
Optimizing Oscillator Power Consumption

• Bias transistors for high transconductance
  efficiency (gm/Id)
• One way to identify the operating region and
  inversion level is inversion coefficient (IC)

(technology dependent)
subthreshold slope factor
where
IC 1 ? Moderate inversion IC gt 1 ? Strong
inversion IC lt 1 ? Weak inversion
18
Transconductance Efficiency
IC 0.01

• Use simulation-based plots for design
• Target region where efficiency gt20 for low power
  design
• Tradeoff Smaller IC means lower ft

Weak inversion (high efficiency)
Center of moderate inversion
Strong inversion (low efficiency)
(simulated results using ST 0.13um models)
19
Power-optimized LC Oscillator
(in fab, back winter 2004)
on-chip inductors
Simulated Performance
W/L240/0.13µm IC 0.01
20
Effect of Vdd Scaling on Oscillator Operation
(Simulations from power-optimized LC oscillator)

• Bias current constant
• Frequency dependence 36.5 MHz/V
• Phase noise constant within 1dBc/Hz
• Output swing also constant

21
Scaling Down Vdd
Some possibilities
Standard LC differential oscillator
Single-ended Colpitts oscillator
Replace tail source with inductor

• Power savings linear with Vdd reduction, but
  little effect on performance for these circuit
  topologies.

22
Proposed Calibration Technique
Is it possible to use an integrated LC oscillator?
Low-accuracy LC oscillator (lt100µW)
High-accuracy (500ppm) FBAR oscillator (300µW)
periodically lock LC oscillator to FBAR reference
Vctrl
FBAR osc
PD
LPF
turn on FBAR oscillator to calibrate
23
Upcoming Work VCO
Vdd
Vctrl

• Test low power oscillator
• Investigate more low Vdd oscillator topologies
• Tape out low power VCO (Feb-Mar 2004)
• Investigate locking VCO with FBAR reference
  oscillator