ECE 444 Assignment 4

1
Assignment 4 Due 20 September 2004

• Goal
• Review Sequential Circuit Design
• Practice Verilog constructs for sequential
  circuit design

• Design a four-bit shift register and control
  unit. The shift register will shift right
  logical, shift left logical, and shift left
  circular depending on the value of the control
  input. An additional input required is the
  number of bits to shift. All shifts are
  sequential and shift one position per clock.
  Develop a state diagram, a state table, and write
  an RTL description of the register control unit.
  Write the Verilog HDL and simulate the register.
• Repeat problem 1 for a four-bit barrel shifter
  (shifts in parallel). The control inputs are
  srl, sll, and shc along with the number of bits
  to shift. The complete shift should consume one
  clock period.