Date:

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Mechatronics Robotics

• Dr Vesna Brujic-Okretic
• Introduction to Microprocessors I
• Room 11cBC03 or MSRR Lab.
• Ext. 9676 or 9681
• Email mes1vb_at_surrey.ac.uk

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A microprocessor

• key element of a mechatronic device
• responsible for
• processing
• storing
• utilising information
• handle data in digital form
• accept binary (or hexadecimal) data formats

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...

• differences from logic circuits etc. include
• programmability
• digital processing
• speed
• ease of integration
• cost

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The history

• first computing machines (modern) 1943
• 1950s - transistor replacing electronic valves
• 1958 - first IC (Texas Instruments)
• 1971 - first true microprocessor
• 1973 - first modern 8-bit mP (Intel 8080)
• 1978 - 16-bit device Intel 8086 - beginning of
  x86 architecture
• main rival Motorola 68000

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Key features

• flexibility and intelligence to devices
• ease with which system can respond to altered
  requirements
• intelligence level determined by its control
  system
• contains hardware and software
• reduction in size an power consumption -
  revolutionary

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One classification

• 1. General purpose computer system
• each PC contains a mP as its main part. They
  differ in memory requirements etc. depending on
  the purpose
• running wide range of tasks and different
  programmes RAM needs to be large need for
  memory management system as well
• primary I/O devices keyboard, mouse, VDU
• 2. Embedded microprocessor
• when part of a larger system, as a sub-system

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Embedded microprocessors

• more specific tasks
• important to select correct mP for the task
• crucial parameters to consider
• performance/
• response time
• cost
• Input/Output
• both analog and digital interfaces to sensors
  actuators
• simple man-machine interface (LED or so) - less
  elaborated

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The architecture of a microprocessor

• basic architecture has not changed much
• there are 3 key elements
• CPU
• Input/Output devices
• Memory
• they communicate via BUSES
• mPs may exist as
• discrete integrated circuits or
• be on a single chip

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mP architecture
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Buses

• Data bus
• may contain 8 lines, typically
• Address bus
• 16, typically
• Control bus
• an arbitrary number (often 15, for example)

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The CPU

• It processes the data by executing a program
  stored in the memory
• It performs sequence of fetch-and-execute
  operations
• It consists of
• Control Unit
• Arithmetic and Logic Unit (ALU)
• Registers

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The CPU

• is responsible for the control of address, data
  and control buses (a master)
• all actions within mP synchronised to the CPU via
  a clock signal
• clock signal
• a logic square-wave to drive all the circuitry
  in the mP
• typical clock frequencies 1 to 30 MHz

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The diagram of a CPU
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The Control Unit

• determines timing and sequence of operations
• generates timing signals which are used to fetch
  program instructions from memory and to execute
  it
• also responsible for decoding instructions
• supplies control signals to read and write data
  into registers, controls ALU and external control
  signals

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The ALU

• The arithmetic and logic unit (ALU) - responsible
  for data manipulation
• arithmetic operations, logic operations (AND, OR,
  etc.)
• bit shifting, rotating, incrementing,
  decrementing and testing

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Registers

• data that CPU currently uses - stored in special
  memory locations on the CPU
• these are called - registers

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Registers

• accumulator register - where data for the input
  to ALU is temporarily stored
• flags register - contains the result of the
  latest process carried out by ALU
• general purpose register - temporary storage for
  data or addresses
• program counter - keeps track opf CPUs position
  in the program

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Registers

• instruction register -stores instruction where it
  can be decoded not accessible by the programmer
• index registers - hold the address of data to be
  used by the program
• stack pointer register - holds the address of the
  top of the stack in RAM. Stack - special area of
  RAM last-in first-out (LIFO) file organisation

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typical CPU register configuration
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Memory organisation

• the address range is allocated to specific
  functions appropriate to RAM and ROM requirements
• this is called - memory map
• we shall talk about all this later
• now, concentrate on the memory devices

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Memory devices

• mP must include memory devices to store binary
  data
• memory takes the form of IC
• family tree of computer memory is shown on the
  following slide

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mP memory devices
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Input/Output devices

• Input
• keyboard
• mouse
• etc.
• Output
• printers
• plotters
• etc.

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Buses

• Data bus. To transfer the data associated with
  the processing function of the microprocessor.
• Address bus which contains the address of a
  specific memory location for accessing stored
  data.
• Control bus. This carries the control signals to
  the memory and the I/O devices.

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mP architecture - reminder
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Buses

• concepts of address and data is fundamental to
  the operation of the mP
• memory - consists of locations uniquely
  identified by CPU through their address
• CPU communicates with those addresses to read and
  write the data - all data.
• the comms go via buses
• the CPU - responsible for control of address,
  data and control buses

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Buses

• data bus
• may contain 8 lines, typically
• address bus
• - 16, typically
• control bus
• an arbitrary number, often 15

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Buses

• all devices attached to data bus - potential
  clash
• devices connected to data buses can be driven to
  high-impedance states
• The ability of devices to set their output at
  either logic 1, logic 0 or in a high impedance
  state is an essential feature of common bus
  systems and is termed a tristate device.
• The read cycle shown in figure 2.2(a) lasts for
  two cycles of the clock signal

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Timing diagrams - read/write cycle
Figure 2.2
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Read cycle

• It lasts 2 cycles of the clock signal
• 1. address of required memory location put on
  address bus (by CPU), at rising edge
• 2. while device held at tristate level -
  control bus issues read signal (active low) to
  the device (2nd cycle begins)
• 3. after delay - valid data placed on data bus
• 4. levels on the data bus sampled by CPU at
  falling edge of the 2nd cycle

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Write cycle

• 1. CPU places address at rising edge
• 2. decoding logic selects correct device
• 3. 2nd cycle - rising edge CPU outputs data
  onto data bus sets WRITE control bus signal
  active (LOW)
• Note
• memory devices other I/O components have static
  logic - so do not depend on clock signal they
  read data from data bus when write signal high
  (inactive) - data must be valid for transition

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typical 64k memory map
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RAM and decoder for 4k memory device
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logic implementation of an address decoder
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summary

• Embedded microprocessors are those which form a
  sub-system of a larger device for example
  microprocessors in consumer products.
• The microprocessor architecture consists of three
  fundamental units memory, CPU and I/O devices
• To convey digital information, the microprocessor
  uses three buses. These are the data bus, the
  address bus and the control bus.

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• The CPU consists of control structures, memory in
  the form of registers and the arithmetic and
  logic unit
• The memory map describes how addressable memory
  in the CPU is organised into physical units. An
  address decoder is used to select the correct
  device by peeking at certain parts of the address
  bus
• There are two broad families of memory devices
  RAM and ROM and each has its advantages and
  disadvantages. ROM tends to be used for
  boot-strapping memory resident programs while RAM
  is used for volatile data storage