Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley

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A Case Study of Synthesis for Industrial-Scale
Analog IP Redesign of the Equalizer/Filter
Frontend for an ADSL Codec
Rodney Phelps, Michael Krasnicki,Rob A.
Rutenbar, L. Richard Carley Carnegie Mellon
University James R. Hellums Texas Instruments,
Inc.
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Why Synthesis? Many SoCs Need Analog
Digital part of a mixed-signal IC Tools support
synthesis, reuse, high-productivity design
Analog part of a mixed-signal IC Still mostly
designed by hand, one transistor at a time
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Motivation

• SoCs use analog to connect to physical world
• Data conversion, sensors, LANs, wireless links
• A small fraction of the chips area--critical
  nonetheless
• Analog today is still mainly designed by hand, by
  experts
• Minimal or ad hoc strategies for reuse and IP
  capture
• Big problems for design times, success on first
  silicon
• Synthesis tools can now successfully design
  analog cells
• But what about systems, which are MUCH larger?

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Analog Synthesis Basic Architecture
Unsized fixed topology
Sized biasedcircuit
Optimization Engine
-
-
Circuit Specs
DesignDecisions
EvaluationEngine

• Optimization-based numerical search
• Optimization engine proposed circuit solution
  candidates
• Evaluation engine evaluates quality of each
  candidate
• Minimizes a cost function to find the best
  design

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Why Most Early Synthesis Tools Failed

• Over-simplified circuit evaluation
• Dont actually simulate each circuit
• Done to make search tractable
• Done to make CPU times tractable
• Problem
• Cannot guarantee resulting circuit will pass
  simulation verification
• Even small analog circuits require a complex mix
  of ac, dc, transient simulations to verify fully

Optimization Engine
Circuit Specs
DesignDecisions
EvaluationEngine
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Our Approach Two Critical Ideas

• Better search
• New, faster numerical algorithm
• Starting-pt independent
• Easy to parallelize
• Runs on pool of CPUs

• Full SPICE sim
• Encapsulation hides simulator idiosyncrasies
• Leverages huge investments in software, models
• Consistent with manual design methodologies

Optimization Engine
EvaluationEngine

• Krasnicki et al, DAC99, Phelps et al, CICC99

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Approach Works Well on Analog Cells

• Production circuits from TI
• A few hours on a CPU farm
• Passes all TI design specs
• Example
• CMOS folded cascode opamp
• 2 hours/run, show 5 runs

Power (mW)
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TI Hand Design
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10
9
26
32
35
38
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UGF spec 162Mhz This ckt 159MHz

Area (1000 sq. grids)
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Next Problem Can We Attack Systems?

• Basic analog systems are hierarchical, and
  composed of
• Analog cells opamps, comparators, bandgap
  refs, etc
• Glue circuits analog switches, passive R,C,
  shared biasing
• Immediate obstacle
• Analog cells are relatively easy to simulate flat
• Systems are not--flat device-level simulation may
  be intractable

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Roadmap for Our Case Study

• Our major goal
• Apply simulation-based synthesis to a real system
  at TI
• Step 1 Select a serious system for a case study
• Describe function, constraints, complexity
  implications
• Step 2 Develop a taxonomy of synthesis
  strategies
• All simulation-based--SPICE-in-loop--but with
  macromodels
• Step 3 Execute a set of synthesis results
• In each style, compare our design against TIs
  complete ckt

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A Serious System TI ADSL Modem Frontend

• R. Hester, et al., CODEC for Echo-Canceling,
  Full-Rate ADSL Modems. IEEE Intl Solid-State
  Circuits Conference, 1999.
• Focus on equalizer/filter (EQF) at frontend of
  modem
• Circuit physically in receiver CODEC at remote
  end (client)

EQF
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EQF What It Does

• EQF equalizer 4th-order elliptical low-pass
  C-T filter
• Programmably amplifies signal (since attenuated
  by copper)
• Filters data from spectrum (avoiding phone voice
  band)

Eq5
Eq4
Eq3
Eq2
Eq1
Eq0
Eq0
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EQF Circuit-Level View

• Top-level 5 low noise amps (LNA),46 Rs, 32
  Cs, 36 switches, 6 modes
• Cell-level LNA is 60 devices
• Total size 400 devices, flattened

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Simulation-Based Synthesis Strategies

• Option 1 Flat
• Flatten the entire EQF down to devices
• Treat it as one (very large) cell, for synthesis
• Option 2 Sequential
• Top-down synthesize abstract system model, to
  explore options
• Bottom-up synthesize the cells, then the
  top-level system
• In either case, we need to use macromodels of
  cells
• Option 3 Concurrent
• Let top-level and cells negotiate,
  simultaneously, right specs
• Again, we need macromodels, but very different
  usage

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Overview How Our Synthesis Works
Choose K random circuit solutions...
2
Add back, kill worst K solutions
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From a population of candidate solutions..
.
1
Repeat until no large change
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Search locally to optimize cost
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Numerical Ideas

• We start with evolutionary algorithms
• Population of solutions helps combat local minima
• Not genetic in strict sense we do no crossover
  ops
• Not just an optimizer--start with no sizing, no
  biasing--none
• We add local evolution via shared annealing
• Each improvement step is a limited annealing
  sequence
• All cost components obtained from full circuit
  simulation
• Some novel mechanics to synch anneal-streams see
  paper
• We parallelize distribute population updates
  over CPUs
• A single circuit eval can require many separate
  simulations
• Tool framework manages distribution, dynamic
  scheduling

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Option 1 Flat Synthesis

• Flat synthesis for EQF intractable
• Flat simulation is feasible, just too expensive
  2-3 hours/ckt
• Even individual specs are expensive to eval
  45mins for THD

Optimization Engine
EvaluationEngine
Too slow
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Option 2 Sequential Synthesis

• Inherently iterative, since some part of
  hierarchy is unknown

System/Cell Synthesis (size bias)
Fix system topology System specs Cell macromodels
Sized Design
Derived Cell Level Specs
Fix cell topology
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Top-Down Synthesis Experiment

• Replace LNA cells with simple macromodels
• Use symbolic model that captures ac behavior, and
  noise
• Replace ckt simulation with model evaluation
  in synthesis
• Modeling methodology
• Assume ideal amplifier, exponential noise falloff
• EQF model top-level circuit LNA models

-Ao
Noise
A(s)
(1s/p1)(1s/p2)
Freq
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EQF Why Noise versus Area Is Critical

• Noise vs area is a fundamental tradeoff
• Why?
• Top-level Rs small but noisy
• Top-level Cslarge but noiseless

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Top-Down Synthesis Results EQF Noise/Area

• Methodology
• Use synthesis to minimize noise for a given area
• Approach can be used to explore the design space
• Resources
• 2 hours total on 20 CPUs

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Bottom-Up Synthesis

• Fix LNA specs, synthesize cells, then synthesize
  top-level EQF
• In general iterative
• In this case, we know workable cell specs from TI
  production IC

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Circuit-Level LNA Opamp Macromodel
Model Parameters
1. DC Gain 2. Pole1 3. Pole2 4. Noise value 5.
Cin 6. Rout 7. Cout No model for distortion
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Bottom-Up Synthesis LNA Results
Superior Synthetic LNA
TI Hand Design
Veff slightly low

• 10hours/run on 20 CPUs, 5 separate synthesis
  runs
• 4 runs met all specs 1 run Veffective slightly
  low on few devices
• All runs within 20 of manual on power and area

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Bottom-Up Synthesis EQF Results
Substitute LNA Macromodel (4 runs)
Synthesize full EQF

• 2 hours/run on 20 CPUs, 5 synthesis runs for
  each full EQF
• Each EQF met all TI specs component values all
  similar toTIs
• Re-verified each EQF inserted full LNA model,
  simulated flat
• Each full EQF met all TI specs

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Option 3 Concurrent Synthesis

• System and components negotiate correct component
  specs

System Synthesis
Want 60dB gain
Search top-level parameters component specs
Add as penalty term to cost, to coerce
convergence
60-57 3
Component Synthesis
Search component device parameters
Got 57dB gain
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Lets Component Specs Evolve Dynamically

• System-level model specs converge to measured
  SPICE values from cells as concurrent synthesis
  progresses
• Simulation-based synthesis used for both cells
  system
• Penalty terms coerce consensus across the design
  hierarchy

Example component spec
SPICE simulation value from LNA cell,
computedduring EQF system synthesis
Output Noise (nV/sqrt(Hz))
Computed difference SPICE value - EQF system
spec goes to 0 as system cells evolve
consensus on specs
Synthesis progress
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Concurrent Synthesis Results

• 10hours/run on 20 CPUs, 3 synthesis runs all TI
  specs met

Max Noise 25-1104KHz _at_25oC (nV/Hz1/2)
TI Hand
Run1
Run3
Run2
Area (1000 square grids)
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Concurrent Synthesis Results Quality
Max Noise 25-1104KHz _at_25oC (nV/Hz1/2)
TI Hand
Run1
Run2
Run3
2 Runs Smaller less noise
1 Run Biggest least noise
Area (1000 square grids)
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Concurrent Synthesis Eq0 Spectral Mask
TI Hand
Run1 Run2 Run3
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Conclusions

• Largest systematic analog synthesis experiment
  ever tried
• State-of-the art TI ADSL frontend EQF correctly
  synthesized
• All synthesized designs qualified exactly as
  industrial design
• All synthesized designs competitive
• Simulation-based synthesis can attack analog
  systems
• Need intelligent application of cell-level
  macromodels
• Need to exploit hierarchy
• Concurrent approach worked best
• Big productivity gain 3 months by hand, 2 weeks
  by synthesis

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