Chapter 3: Logic Levels and families

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Chapter 3 Logic Levels and families
Logic Design(CS33)

• Ms Veena V Desai
• Assistant Professor
• Department of Electronics and Communication
  Engineering
• Gogte Institute of Technology
• Udyambag, Belgaum-8. INDIA.
• Email karchiveena_at_yahoo.com

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Session 1

• Logic Levels
• Logic Families
• Integration Levels
• Switching Times
• Propagation Delay
• Fan-in and Fan-out

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Binary Logic Values

• Logic 1
• Logic 0
• Undefined value

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Logic Levels

• Positive Binary Logic System
• High level - logic 1
• Low level - logic 0
• Negative Binary Logic System
• High level - logic 0
• Low level - logic 1

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Positive and Negative Logic
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TTL Logic Levels

• Logic 1 - VH
• 2.4V? VH ? 5V
• Logic 0 - VL
• 0V? VL ? 0.4 V
• Undefined
• 0.4 V lt V lt 2.4 V

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TTL Logic Levels

• Floating signals may take on illegal values
• What happens during a signal transition?

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Classification of Logic Families

• Logic families are classified based on
• Devices Used
• example diodes ,transistors etc.
• Structure of Digital Circuits
• example MOSFET(PMOS,NMOS)

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Examples of Logic Families

• DTL Diode Transistor Logic
• RTL Resistor Transistor Logic
• TTL Transistor Transistor Logic
• ECL Emitter Coupled Logic
• CMOS Complementary MOSFET Logic

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Logic Families Differ In

• Logic Levels
• Propagation Delays
• Driving Capabilities
• Other Parameters

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Electrical Characteristics of Logic
Families(Noise margins)

• VOHmin min value of output recognised as a 1
• VIHmin min value input recognised as a 1
• VILmax max value of input recognised as a 0
• VOLmax max value of output recognised as a 0
• Values outside the given range are not allowed.

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TTL and CMOS(basic structures)
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TTL and CMOS(Characteristics)
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Integration levels

• SSI -small scale integration
• MSI -medium scale integration
• LSI -large scale integration
• VLSI -very large scale integration
• ULSI -ultra large scale integration
• GSI -giant scale integration

Complexity of a single chip is called Scale of
Integration.
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Integration Levels (comparison)
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.contd
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Switching Time
tf
tr
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Output Switching Times

• tLH- low to high rise time (tr)
• Time interval between 10 to 90 of Vdd
• tHL- high to low time or fall time (tf)
• Time for signal to fall from 90Vdd to 10Vdd

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Maximum Switching Frequency

• Switching is fast with
• tminthltlh
• Max switching freq is given by fmax1/tmin
• Eg thl 0.5 nsec, tlh1.0 nsec
• tmin 1.5 nsec
• fmax1/ tmin666.67Mhz

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Propagation Delay

• It is the physical delay as the logical signal
  propagates through the gates.

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tplh and tphl

• tplh-is the propagation delay component for an
  output high to low transition.
• It is the time which elapses from the instance
  the input reaches 50 of VDD to the time the
  output reaches 50 of VDD.
• tphl is the propagation delay component for an
  output low to high transition.

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Fan-out

• Fan-out of a gate is the number of gates driven
  by that gate i.e the maximum number of gates
  (load ) that can exist without impairing the
  normal operation of the gate.

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Fan-out Of Inverter
No Load Fan-out is 0
Load Fan-out is 1
With 3 inverter loadFan-out is 3
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Fan-in

• Fan-in of a gate is the number of inputs that
  can be connected to it without impairing the
  normal operation of the gate.

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Fan-in Of a gate

• Number of inputs to a logic gate
• example for NAND gate with n inputs
• n 2 Fan-in2
• n 3 Fan-in3
• n 4 Fan-in4

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Other details to be considered

• Extension of propagation delay concepts to other
  logic gates. egAND gate, OR gate.
• Effect of Fan-in and Fan-out on logic cascades.

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Summary

• Interpreted Logic Levels
• Differentiated and Compared Logic Families
• Defined Switching Times,Propagation Delay ,
  Fan-in and Fan-out
• Examples