Ch'3 Overview of Standard Cell Design

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Ch.3 Overview of Standard Cell Design
TAIST ICTES Program VLSI Design
Methodology Hiroaki Kunieda Tokyo Institute of
Technology
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• 4.1 Basic Components

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Design Method

• Standard Design --------- Design by makers spec.
• Full Custom Design ------ Design of all masks by
  customers spec.
• Manual Design
• Cell-Based Design
• Custom Cell/ Full Custom Design
• Standard Cell Design
• Semi Custom Design ----- Design of routing wire
  logic functions by customers spec.
• Gate Array
• FPGA Design

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Standard Cell Design
Logic gates, latches, flip-flops, or larger logic
Routing channels
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Standard Cell Design

• Design Using Standard Cell, pre-design by
  professionals.
• Cells includes Verilog, Circuit, Layout
  Information for NAND, NOR, D-FF
• Logic Design and Layout Design done by CAD.
• Logic Design --- by use of Cells with specified
  delays
• Layout Design by use of Cells
• Generated Data is mainly interconnection wires.

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Logic Design
RTL Simulation
RTL
Logic Synthesis
Synthesis Netlist
Functional Verification
Scan Path Design
Functional Verification
Scan Netlist
Timing Analysis
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Layout Design
Netlist
Layout Design
Functional Verification
Gate Level Simulatior
Layout Netlist
ATPG
Mask Data
DRC/LVS
Test Pattern
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Standard Cell Library

• Circuit description at RTL level
• Layout description in GDSII format
• TLF Format Data
• Logical information
• Transistor and interconnect parastics
• Spice netlist
• Power information
• Process, temperature and supply voltage

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Standard Cell Library Design Flow
Layout Design
Mask Data GDSII
Abstract Generator
Library Data LEF
Cell Information Technology information
Extraction
Circuit Data Netlist
I/O delay paths Timing check values Interconnect
delays
Analog Environment
Circuit Data TLF
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Vertical and Horizontal Grids
Legend
Vertical Grid
Horizontal Grid
Cell Origin
PR Boundary
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List of Standard Cells

• D Flip-Flop w/S, R, Q, Q
• Clocked Latch
• Delay Cell
• D Flip-Flop w/Asy, R, Q
• AND/OR MUX
• Exclusive OR
• Stackable Shift Register
• Stackable Two Phase Clock Driver
• Wiring Via
• Power Pad
• VSS-Diode Only Input Pad
• Schmitt Triggered Input Pad
• Tri-State I/O Pad
• Tri-State Output Pad

• Dual Inverter
• 2-Input NOR
• 2 NAND
• Inverter
• Non-Inverting Buffer
• Tri-State Buffer
• Data Select
• Transmission Gate
• NAND Latch
• Pull-Up
• Pull-Down
• 4X Inverting Buffer
• Hi-Impedance Buffer
• AND/OR MUX
• Exclusive OR

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Inverter Gates
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NAND Gates
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Design Flow
VHDL Model
VHDL -gt Verilog Conversion
Synopsys Design Compiler
Verilog Model
Standard Cell Placement
Cadence Design Planner
DEF File
Standard Cell Routing
Cadence Silicon Ensemble
DEF File
Export to Other Formats, SPICE Verification
Cadence ICFB
Verilog Model
Verilog Verification
Modelsim
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Silicon Ensemble

• Cadence Layout Tool
• Import a Verilog netlist into Silicon Ensemble.
• Floor Planning

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After Floorplan Initialization
double height cells supply rings that are between
the I/O and Core sections.
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PAD Placement
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Corner Pad Placement
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Placing Cells (Qplace)
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Adding Filler Cells (Silicon Ensemble)
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Wroute (Silicon Ensemble)
Routing is completed.
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ICFB (Layout Editor)