Improving IJVM Performance

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Improving IJVM Performance

• Rev up the clock speed
• Redesign circuits to reduce delay, e.g.
• Use ripple adder decrease worst-case ALU
  propagation
• Reorder some microinstructions, e.g.
• Do something useful during memory delays
• Grab work from next machine instruction
• Add an incrementer to PC register
• Eliminate decoder for B bus
• Note tradeoff among speed, cost, and space

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More Improvements

• Add a bus for A side of ALU
• Do fetch separately pre-fetch in batches
• This is really a simple two-stage pipeline
• Find parallelism (the wall is serial tasks)

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Still More Improvements

• Pipeline around ALU (3 stages)
• Note pipeline enables faster clock too
• Add lots of registers (a RISC-y thing to do)
• Add level(s) of cache
• P4 has a trace cache for micro-ops
• Add smarter decoding, e.g.
• Go superscalar
• Dispatch/route as you decode

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Pipelines and Control Signals
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Pentium II Dispatch/Execute Unit
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UltraSPARC II Microarchitecture
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UltraSPARC II Pipeline
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Even More Improvements

• Add branch prediction
• Track history (works like cache)
• Allow two misses before switching prediction
• Out-of-order execution
• Register renaming enables multiple versions
• Scoreboards track which registers instructions
  use
• What about interrupts?
• Pentium 4 reorders execution only, not
  issue/retire
• Speculative execution (like EPIC)

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Out of Order Scoreboard
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Pentium 4 Path
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Possibly Even More Improvements

• IJVM is really kinda CISC-y
• RISC might skip most of this micro-sequencing
• Note how P4 does it both ways (ROM is optional)
• Symmetric MultiProcessor (SMP)
• Shared RAM, but separate caches (coherency
  issues)
• Alternatives clusters/blades, NUMA/CC-NUMA
• Hyperthreading (or Simultaneous Multi-Threading)
• Something between superscalar and multicore
• Dispatch instructions from collection of threads
• Vector processing (SIMD single instr, multiple
  data)
• Multicore share outer cache, separate inner
  cache(s)

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SMP
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Cluster
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CC-NUMA
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Hyperthreading and Multicore
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Multicore Chip Organization