Weekly Research Progress

1
Weekly Research Progress

• Hwang, Woo-Min
• August 14th, 2004 August 20th, 2004

2
Progresses Plan

• Progresses
• Digital Design Flow Education (8.14)
• Digital Clock Synthesis (2nd week of 4), at
  Chonbuk N. Univ.
• Hynix 0.25? Process Explanation (8.18)
• AVR Core
• VHDL Code Analysis (Peripheral Control Registers
  / Timer)
• Verilog coding
• CoreCom II
• JPEG picture display with Geode SC1200 EVM
  complete

3
Progresses Plan

• AVR Core
• 12 files in the VHDL AVR Core
• External_mux.vhd is completed
• Simple_timer.vhd / Service_Module.vhd is analyzed
• Verilog coding is under way.
• CoreCom II
• Video Team Install whole X-window library
• RedHat 8.0 full installation

4
Progresses Plan

• Plans
• Digital Design Flow education (8.21)
• 3rd Week at Chonbuk N. Univ.
• SDF file extraction / Place Routing
• Timer_Counter.vhd of AVR Core analysis
• AVR Core schedule
• 8.1 9.30 Core Analysis and development
• 10.1 10.31 Design Verification
• 11.1 Tape Out Due