Introducing the Cierto Signal Processing Worksystem V4'5 May1999

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Introducing the Cierto Signal Processing
Worksystem V4.5 May1999
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A complete Signal Processing System Design
Verification Environment

• SPW for System Design
• Algorithm Evaluation Optimization for HW SW
  using SDF model
• Rich application-specific libraries analysis
  tools
• Environmental models (channels, sensors)
• SPW for IP Creation
• Graphical, parameterized IP
• Reusable self documenting
• Efficient RTL generation for ASIC or FPGA
• C code generation for SW
• SPW for Verification
• Application-specific testbenches
• ASIC verification in the context of the system

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Whats New in SPW 4.5

• Extended Flow
• SPW/NC Sim Link for System/ASIC co-development
• Efficient RF/Baseband system verification
• Model export to VCC for IP reuse platform
  integration
• Enhanced Comms and Multimedia Libraries for
  leading-edge applications
• Target WCDMA digital video
• Simulation Speed and Capacity Increases for
  multimillion gate designs
• 2x to 5x simulation speed increases
• 60 HDL generation capacity increase
• Productivity Enhancements
• Polymorphic technology for data type independent
  blocks
• Block wizard simplifies creation and import of IP
• Full compatibility with previous release

SPW 4.5 delivers new level of flow integration
and productivity