GaNonDiamond Why'''

1
GaN-on-Diamond Why... How Felix
Ejeckam November, 2006
2
In trying to solve the heat-problem, weve
considered the following facts

• Heat is a well-known performance terminator in
  transistor physics,

• Much of the heat comes from the active junction
  (just a few microns thick), and

• Access to the active junction could enable
  effective and efficient heat extraction.

3
Weve developed a new GaN wafer !

• that places the FETs junction just 10s to 100s
  of nms from a near-perfect thermal conductor
  (diamond), and

• GaN
• Ideal for high-power High-Temperature
• Proven Materials System
• Proven Transistor Technology
• Using low-cost GaN-on-Silicon

• Enables devices
• With best-in-class performance ! (e.g. FETs,
  LEDs, etc.)
• Never before made ! e.g. high powered UV/Blue
  LDs

• Atomic
• Attachment Technology
• Scalable to other materials e.g. InP-,
  on-Diamond, etc.
• Also scalable to 6, 8, 12, etc.

• that enables heat extraction via physical
  conduction and heat-spreading !

• CVD DIAMOND
• Natures best thermal conductor
• Natures best electrical insulator
• Natures toughest material
• Available in low-cost

4
And heres how we make GaN-on-Diamond wafers
GaN FET Epiwafer
5
Today, we develop GaN-on-Diamond FET epi-wafers
for FET/HEMTs!
6
Various thermal simulation models reveal the
promise of GaN-on-Diamond wafers

• FET Junction Temp vs. Substrate Thermal
  Conductivity

• FET Power vs. Substrate Thermal Conductivity

7
THERMAL MODEL STRUCTURE
Array of linear heat-generating devices on
GaN (length of heat sources is long in comparison
with the separation d and width of the sources)
TP
d
?T TPT0
GaN epilayers
T0 23C
y
substrate
z
8
THERMAL MODEL STRUCTURE
0.5 µm
linear-heat-source separation D
0.2 µm
0.2 µm
Layer 1 GaN (1 µm) ? 1.3 W/Kcm
Layer 2 AlGaN buffer layer (1 µm) ? 0.8 W/Kcm
Substrate
y
z
9
SUBSTRATE THICKNESS ASSUMPTIONS
10
With Diamond, you could reduce the pitch to
10-mm, and still see the temperature drop 100C
compared to SiC!
Gate input power 10-W/mm Substrates bottom
temp 23C
11
and at 50-W/mm, with a 20-mm pitch, the temp
drop is gt500C compared to SiC!
at high-temp, other effects may set in
Gate input power 50-W/mm Substrates bottom
temp 23C
12
At powers over 25 W/mm, diamond drops the GaN
junction temp by 100C
Gate-to-Gate Pitch 50mm Gate input power 10-W/mm
13
And, why not just solder GaN to diamond?

• because junction temperatures are highly
  sensitive to a substrates thermal conductivity,

• Just a 25-mm thick solder b/w the GaN junction
  and diamond could consume nearly all the thermal
  benefits of diamond

• Case Study A 3-mm GaN buffer beneath the epi
  would elevate the junction temperature by 42

14
SOME TAKE-AWAYS

• Diamond could drop a GaN FETs junction
  temperature by 20C per 0.1-W/mm of dissipate
  power !

• Assuming a FET-to-FET spacing of 40mm, and
  gate-power of 10-W/mm, diamond could drop the GaN
  junction temperature by 135C compared to SiC !

• Diamond at (almost) any thickness offers a
  dramatic improvement over SiC the thicker the
  better !!

15
EXPERIMENTAL VERIFICATION

• GaN-on-Diamond FET development is underway with
  several partners, and .

• Meanwhile, some simple platinum resistors have
  been fabricated on GaN-on-Diamond wafers to demo
  diamond impact on temperature.

16
A resistor-based experiment was devised to i)
generate FET-like power on a GaN-on-Diamond wafer
surface, and ii) measure surface temperature
changes associated with the power.
RESISTOR EXPERIMENT SETUP
DC power supply
Resistance meter (via Power)
GaN FET Epi layer (1-2mm)
Substrate (various)
Platinum lines to simulate heating resistor
Heat sinking chuck No adhesive is used for
substrate mounting
17
Excellent quality platinum resistor lines were
fabricated atop the GaN-on-Diamond wafers.
PLATINUM RESISTORS ON GaN-on-Diamond
Platinum lines for heating
Platinum contact pads
GaN surface
18
A 3X boost in substrates thermal conductivity
3X reduction in substrates thermal impedance
RESISTOR RESULTS
Substrate
Heat sinks
19
Diamond drops the resistors thermal impedance by
58 while ALSO allowing a 3X boost in power
density !!
RESISTOR RESULTS
20
Our diamond process affects little the GaN
epitaxy !!
PRELIMINARY FET RESULTS
21
What does the early data tell us ?

• Diamond could drive down thermal impedance (C/W)
  by gt58 (maybe more after optimization)
  compared to SiC !

• AND Diamond could drive up a GaN FETs power
  density 3-fold compared to SiC

• Poor mounting and packaging could limit the
  benefits of diamond !

22
The End
23
Appendix
24
And heres how we make GaN-on-Diamond wafers
25
DEVICE STRUCTURE ASSUMPTIONS

• Length of each chip (L) 3mm
• Gate length (W) 150-microns
• Carrier beneath the substrates is assumed to be
  an infinite and perfect thermal conductor
• Chip Power Density presented here is defined as
  Watts per Area (LW) given a devices (active
  junction) maximum allowable operating temperature