Victor Varshavsky

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Victor Varshavsky
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A bit of history
G.B. Vico -1650 (courtesy of ASV)
The Age of the Gods SENSES
The Age of the Heroes IMAGINATION
The Age of the Men REASON
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Old Testament (1976)
Basic blocks with completion (flip-flops,
registers, combinational)
Implementation of control (direct translation)
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Asynchronous latches
S
Q
Classic RS-latch observing outputs cannot tell
if operation is completed
Q
R
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Asynchronous latches
S
S
Q
Q
Ack
Ack
Q
R
Q
R
Req
Similar structure Armstrong et al 1968
Req
Active
R/S
Q/Q
Req
Ack
Ack-
Idle
RS1
Req-
QQ1
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Two-phase asynchronous FSMs
Combinational Logic (dual-rail)
Asynch register
Completion detector
Ack
Req
Nielsen94, NCL (Fant96), Phased Logic
(Linder96)
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Synthesis by Direct Translation
Idea direct mapping of a behavioural
specification into a modelling self-timed
circuit. Mapping is done at the level of the
control flow skeleton. Advantages (w.r.t. logic
synthesis) linear complexity of the procedure
and transparency of the logic structure.

• Control is defined by, e.g.
• Parallel Asynchronous Flow Charts (PAFCs)
• Petri nets (PNs)

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Places and David cells

• Each place is modelled by a memory latch (David
  cell)

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One of possible translation styles (1996)
join
XOR-merge
controlled choice
fork
Also developed translation for Inclusive-OR
fragments
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New Testament (1986)
Think big
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Self-synchronizing Codes (1981)
Formal conditions for valid code transitions
Single-phase - Direct Transitions (?-partition-
Tracey1966) - Transition-based signaling

• Two-phase
• 2-rail (Akers1961)
• Berger codes (1961)
• k-out-of-n codes

Hardware implementation for coding/decoding
Bainbridge02 (Chain), Worm05
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Self-Repair and Fault-Tolerant Architectures
(1980)

• Fault-detection methods
• Self-repair for regular structures (see later)

Pieter Hazewindus92, Peter Beerel94
A hot topic for future unreliable transistors
(related e.g. to fault detection methods from
W.Jang A.Martin SEU Tolerant QDI Circuits) .
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Fault-Tolerant Self-Timed Ring(1981-1988)
For an onboard airborne computer-control system
which tolerates up to two faults. Self-timed ring
was a GALS system with self-checking and
self-repair at the hardware level
Individually clocked subsystems
Self-timed adapters forming a ring
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Communication Channel Adapter
Much higher reliability than a bus and other
forms of redundancy MCC was developed
TTL-Schottky gate arrays, approx 2K gates.
Data (DR,DS) is encoded using 3-of-6 Sperner code
(16 data values for half-byte, plus 4 tokens for
ring acquisition protocol) AR, AS
acknowledgements RR, RS spare (for self-repair)
lines
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Functional completeness for speed-independent
circuits
Problem Semi-modular State Graph
asynchronous circuit constructed only from 2NAND2
000
100
010
110
011
111
Difficulty hazards under I/O mode

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Functional completeness for speed-independent
circuits
000
Distributive graphs
100
010
Semi-modular graphs

110
011
111

There is no crucial technological limitation to
implement any SI circuit
But how?
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Dreaming of CAD
First attempt SG-based analysis Frazer
Muller, 1960
SI-analysis Reachability analysis based
on Characteristic Functions Varshavsky et al 1980
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Checking Speed-independence
State Graph
a c
SI-conflicts
a
101
100
b c
000
110
111
001

c
c a b
010
011
b
SI-conflict 1 - 1 V 0 - 0
Speed-independence ? no reachable SI-conflicts
(Muller56,60)
Analysis automation

• Ri set of states that can be reached in i
  transitions
• Reach fixed point when Rn Rn1
• Guaranteed since state space is finite

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From Analysis to Synthesis
FORCAGE SI-analysis Event and State based
Verification and State based Synthesis Varshavsky
et al 1990
SI-analysis Reachability analysis based
on Characteristic Functions Varshavsky et al 1980
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Gaining efficiency
Too many states!!!
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FORCAGE to the Future

• The ideas of
• OR-causality,
• Direct translation,
• Decomposition based synthesis,
• Traversal based on Characteristic Functions, etc
• were used in successive asynchronous design
  CAD tools (e.g. Petrify) and still provide a lot
  of room for future research

FORÇAGE is French for afterburner (same meaning
in Russian)
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A bit of magic
I saw the angel in the marble and carved until I
set him free
Michelangelo Buonarroti
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Self-timed pipeline registers (1986)

• dense e.g. Data0-Data0-Data1-Data1
• can have max n data items (most difficult)

Spacer states
Data states
FurberDay96
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Self-Timed FIFO (1988)
Basic FIFO are connected using a wagging-tail
buffer method
Read mux
Basic FIFO
Buffer registers
Write demux
Throughput doesnt depend on the delay of Basic
FIFO.
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Self-Timed FIFO
Address Generation Circuit
ChelseaNowick01
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Back to the Future
Circuits insensitive to delays in transistors and
wires (1987) Idea 1 Modified routing (acking
by field) Idea 2 Make all inputs changes
visible at outputs
Logic to do reversible computations!!!
LaFreidaManohar04
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Logic Design and Quantum Challenge (1996)
Quantum dots
C-element rather than majority gate
Logic optimizations abstracting quantum nature
were proposed
Tunneling transistors
Multi-value (MV) logic
MV logic synthesis
Brayton97, Olsen99
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Beta-driven Threshold Elements
Threshold function
output
Vout
5-input majority element SPICE simulation
Applied CMOS artificial neurons Adders
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Beta-driven Threshold Elements
output
Vout
Vout
n-input C-element
SPICE simulation
(2 transistors per input)
Beiu03
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Thinking of Time
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Thinking of Time
Time is money
Time is relative
Logical time
Physical time
Victor(y)
Events causality
Independent physical variable
Time does not exist if nothing happens
(Aristotle)
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Globally Asynchronous Locally Arbitrary
(GALA,1995)
Synchronous (Master-Slave two-phase clock)
Asynchronous
Pk F(P(k-1, t), P(k,t-1), P(k1,t))
T1
T2
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Globally Asynchronous Locally Arbitrary
(GALA,1995)
Synchronous (Master-Slave two-phase clock)
Asynchronous
Pk F(P(k-1, t), P(k,t-1), P(k1,t))
T1
T2
Applications
Counters with constant response time Arbiter-free
counterflow pipeline
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GALA Impacts
Before
Synchronous
Asynchronous
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GALA Impacts
After
Further development
- Doubly-latched pipelines (Kol
Ginossar,1996) - De-synchronization (Cortadella
et al, 2003)
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Thank you!!!