Turbo Codes and Its Application in Power Reduction

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Turbo Codes and Its Application in Power Reduction

• Victor Wen
• Dec. 14, 2000
• CS294-5/Stat 242A
• Fall 2000

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Outline

• Motivations
• General coding setup
• Turbo Code graphical model
• Simulation results
• Future work/Conclusion

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Motivations

• Turbo Codes used for low-power communication with
  moderate complexities
• Interconnect on chip IS a communication channel
• Increasing importance of wires relative to
  transistors
• Spend transistors to drive wires more
  efficiently?
• Try reduce signal power on wires to save power
  and correct errors due to noise
• Orthogonal to other power-saving techniques
• e.g. transition reduction
• clock gating
• Parallel function blocks (like vectors!)
• Important for portable devices where power and
  energy is a major constraint

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Power Reduction through coding
Encoded Value
Output
Input
Decoder
Encoder

• Can we encode information in a way that we can
  reduce driving voltage?
• Do this on chip?!
• Two possible architectures
• Parallel encoder/decoder runs at same frequency
  but doubles the wire count ? more wire
  capacitance
• Serial only 1 wire(!) for entire bus. But
  encoder/decoder runs at much higher frequency.

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Graphical Model

• U1, U2, Uk represents input bits. X1, X2, X2k
  represent codeword
• S0, S1, Sk represents Markov states
• The code consists of two Markov chain running
  parallel, with input to one chain randomly
  permuted.

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Evaluation Turbo Code simulation in Matlab (1)

• Simulation setup
• Log-MAP decoder, rate ½
• frame size varies from 32, 16 to 8
• signal-to-noise ratio ranging from 1.0 to 2.5
• simulation stops when there are 15 error frames
• Iterations ranging from 1 to 5
• Higher iteration ? lower bit error rate (BER)

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Evaluation Turbo Code Simulation (2)

• For a given signal-to-noise ratio and iteration,
  smaller frame size produces better BER
• Most BER ranges from 0.1 to 0.001. This might be
  too large for communication on chip. However,
  noise ratio should be smaller than free space
• For higher signal-to-noise ratio, the simulation
  runs for a long time before encountering
  sufficient frame error to terminate

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Conclusion Future Work

• Conclusion
• ECC technique seems feasible to reduce power on
  wire
• Turbo codes can be used for small frame sizes (8,
  16 and 32) with sufficiently low BER given high
  signal-to-noise ratio
• Two possible architectures parallel and serial.
  Serial architecture seems more feasible (reduced
  wire capacitance)
• Orthogonal to other low power techniques
• Future work
• Actual evaluation of power dissipated by the
  coding process
• Understand the noise level of interconnects on
  chip to evaluate the optimal voltage reduction
• Adaptively changing the coding rate to cope with
  transient noise level