Efficient Encoding Scheme for UltraFast Flash ADC

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Efficient Encoding Scheme for Ultra-Fast Flash
ADC

• Jayanta Choudhury (Student)
• University of Louisiana at Lafayette
• G. H. Massiha (Asso. Professor)
• University of Louisiana at Lafayette
• ?????
• ??95662001

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OutLine

• Abstract
• Introduction
• Basic TIC Operation
• Encoder Design
• Conclusion
• References

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Abstract

• High-speed ADC needs a fast comparator,a
  high-speed encoder, and a fast sample and hold
  (S-H) circuit.
• The speed of encoders has been dealt mostly on
  the algorithmic part.
• We propose an efficient encoding scheme to be
  designed using robust principle of Programmable
  Logic Array (PLA) for ultra-fast flash Analog to
  Digital Converter (ADC).

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Introduction

• Most of the high-speed ADC design emphasize on
  the issues related to comparator speed, noise,
  offset and quantization error etc.
• The ADC using the proposed comparator claimed to
  have speed (about 1GHz).
• The comparator design was based on the ßn/ßp
  ratio of the inverter to set the reference
  voltage of the comparator.
• Usually these encoders need multiple layers of
  logic gates. Multiple layers of logic gates can
  cause enough delay in signal transition, which
  might diminish the benefits of ultra-fast
  comparators like TIC.
• We propose a novel encoding scheme, which uses
  simple principle of PLA to implement the encoding
  operation.

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Basic TIC Operation
6
Encoder Design
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Conclusion

• We proposed a novel design for an efficient
  encoding scheme for ultra-fast flash ADC with
  schematic diagram.
• It can be concluded that this scheme needs much
  lesser number of gates.
• This saves area and also power as lesser gate
  means lesser paths of power dissipation.

10
References

• 1 Jincheol Yoo Daegyu Lee Kyusun Choi
  Tangel, A. Future-ready ultrafast 8bit CMOS ADC
  for system-on-chip applications, Proceedings 14th
  Annual IEEE International ASIC/SOC Conference
  Page(s)455-459 Arlington, VA, Sept 12-15, 2001
• 2 Daegyu Lee Jincheol Yoo Kyusun Choi
  Ghaznavi, J.Fat tree encoder design for
  ultra-high speed flash A/D converters, The 45th
  Midwest Symposium on Circuits and Systems Vol 2
  Page(s) 87 -90, Tulsa, Oklahoma, Aug 4-7, 2002
• 3 Zhiqiang Gu Sneigrove, W.M. Analysis and
  design of adaptive selftrimming technique for A/D
  converters, IEEE International Symposium on
  Circuits and Systems. ISCAS 94, Vol5, Page(s)
  455-459, May 30-Jun 2, 1994
• 4 N.H.E. Weste and Kamran Eshreghian,
  Principles of CMOS VLSI Design A System
  Perspective, 2rd ed. New Delhi, India
  Addison-Wesley, 2000.
• 5 Roovers, R. Steyaert, M.Design of CMOS A/D
  converters with folding and/or interpolating
  techniques, IEEE International Symposium on
  Circuits and Systems. ISCAS 96, Page(s) 76-81,
  Jul 6-8, 1994
• 6 Cauwenberghs, G. Temes, G.C.6. Adaptive
  calibration of multiple quantization oversampled
  A/D converters, IEEE Second International
  Conference on Advanced A-D and D-A Conversion
  Techniques and their Applications, Vol1 Page(s)
  512-516, May 12-15, 1996