Datapaths but first Keyboard

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Datapaths(but first Keyboard Video)

• Anselmo Lastra

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Today

• Peripherals
• How PS/2 keyboards work
• VGA and basics of video
• Chapter 7 Datapaths
• Basic definitions today

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PS/2 Keyboard

• Uses a synchronous serial protocol
• What does that mean?

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Physical Interface

• Two lines
• Clock (10-20KHz)
• Data
• Pulled high by resistors
• Asserted low
• Takes away your pushbutton unless you do clever
  stuff

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Bidirectional

• Kybd-to-host and host-to-kybd on same wires
• CAPS LOCK light for example
• To send, host takes data line low
• Sometimes take clk low first
• Then kybd starts clocking
• Host sends data synced to kybd clock
• You shouldnt need to send to kybd

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Protocol

• 11 bits
• Start always 0
• 8 bits of data
• Odd parity bit
• Stop bit always 1
• Clocked by keyboard
• Value should be latched on negedge of keyboard
  clock

Illustration from http//www.beyondlogic.org/keybo
ard/keybrd.htm
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What is Sent

• ASCII is not sent
• Scan codes for keys
• Least significant bit first

Illustration from http//www.beyondlogic.org/keybo
ard/keybrd.htm
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Scan Codes

• Normally translated by software
• You remap your keys, for example
• Software takes care of
• Shift, caps lock, control

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Some Scan Codes Long

• Two code sequence common
• Have a look at Break key!

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Even More Complicated

• Scan code generated when you press
• And when you release
• Two codes F0 followed by key scan code
• Example
• Space pressed, 29 sent
• Space released, F0 29 sent
• If you hold key, scan code repeated

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Resources

• Web pages
• http//www.beyondlogic.org/keyboard/keybrd.htm
• http//govschl.ndsu.nodak.edu/achapwes/PICmicro/P
  S2/ps2.htm
• Scan codes
• http//panda.cs.ndsu.nodak.edu/achapwes/PICmicro/
  keyboard/scancodes2.html
• There is also Verilog for keyboard interfaces
  available on web. Much more complex than yours!

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Lab

• Make circuit to read from keyboard
• Latch output scan code
• Suggestions
• Always use master clock for FFs
• always_at_(posedge clk)
• Synchronize keyboard clock
• always _at_ (posedge clk)
• ps2_clk_s

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How?

• I would (did) use
• Shift register to shift bits in
• Counter to count 11 bits
• Counter for timeout
• Reset bit counter if no activity for time longer
  than it takes for scan code to be sent
• Used derived 25MHz clock to make it easier to
  probe signals

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How Do Monitors Work?

• Origin is TV, so lets look at that
• Relies on your brain to do two things
• Integrate over space
• Integrate over time

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Dots to a Picture

• Brain can make this into something recognizable

Images from howstuffworks.com
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Many still Images

• Video (and movies) are a series of stills
• If it goes fast enough
• 50-60 Hz or more to not see flicker
• Your brain interprets as moving imagery

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Simple Scanning TV

• Electron beam scans across
• Turned off when
• Scanning back to the left (horizontal retrace)
• Scanning to the top (vertical retrace)

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Inside TV
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Deflection Coils
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Scanning

• TVs use interlacing
• Every other scan line is swept per field
• Two fields per frame (30Hz)
• Way to make movement less disturbing
• Computers use progressive scan
• Whole frame refreshed at once
• 60Hz or more, 72Hz looks better

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Color

• Three colors of phosphor
• Beams hit each
• Black beam off
• White all on

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Aside

• Frustrated with Verilog
• See what to do to relieve stress
• http//entertainment.howstuffworks.com/what-if-sho
  ot-tv.htm
• Educational too

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VGA Signaling

• RGB and two synchronization pulses, horizontal
  and vertical

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VGA Timing

• Monitor synchronizes with input in more complex
  way than keyboard
• You supply two pulses, hsync and vsync, that let
  the monitor lock onto timing
• One hsync per scan line
• One vsync per frame

Image from dell.com
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Horizontal Timing Terms

• hsync pulse
• Back porch (left side of display)
• Active Video
• Video should be blanked (not sent) at other times
• Front porch (right side)

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Horizontal Timing

• 640 Horizonal Dots
• Horiz. Sync Polarity NEG
• Scanline time (A) 31.77 us
• Sync pulse length (B) 3.77 us
• Back porch (C) 1.89 us
• Active video (D) 25.17 us
• Front porch (E) 0.94 us

Image from http//www.epanorama.net/documents/pc/v
ga_timing.html
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Vertical Timing (note ms, not us)

• Vert. Sync Polarity NEG
• Vertical Frequency 60Hz
• Total frame time (O) 16.68 ms
• Sync length (P) 0.06 ms
• Back porch (Q) 1.02 ms
• Active video (R) 15.25 ms
• Front porch (S) 0.35 ms

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Timing as Pixels

• Easiest to derive all timing from single-pixel
  timing
• How long is a pixel?
• Active video / number of pixels
• 25.17 us / 640 39.32ns
• Conveniently close to 25 MHz just use that
• I calculated some, but also see
• http//www.epanorama.net/documents/pc/vga_timing.h
  tml

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Color Depth

• Voltage of each of RGB determines color
• 2-bit color here (4 shades)
• Turn all on for white

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What To Do?

• Make Verilog module to generate hsync, vsync,
  horizontal count, vertical count, and signal to
  indicate active video
• Use that from higher-level to drive RGB using
  counts gated by active
• Later will use memory addressed by counts
• For now do something simple

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Links

• VGA Timing
• http//www.epanorama.net/documents/pc/vga_timing.h
  tml
• http//appsrv.cse.cuhk.edu.hk/ceg3480/Tutorial7/t
  ut7.doc
• Code (more complex than you want)
• http//www.stanford.edu/class/ee183/index.shtml
• Interesting
• http//www.howstuffworks.com/tv.htm
• http//computer.howstuffworks.com/monitor.htm

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Back to CPUs

• Datapath
• The registers and logic to perform operations on
  them
• Control unit
• Generates signals to control datapath

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Memory and I/O

• Are connected to the data/control in and out
  lines
• Example register to memory ops

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Microoperations

• Basic operations of the datapath
• Example moving data from one register to another
• Not necessarily microprogrammed control
• Microoperation expected to complete in one clock
• Register transfer notation, next

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Register Transfer Language (RTL)

• Registers named in uppercase
• PC, IR (instruction), R3
• Little endian

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RT

• Transfer from R1 to R2
• R2 ? R1
• R2 is destination
• R1 is source
• Conditional
• If(K1 1) then (R2 ? R1)
• K1 R2 ? R1 as a shorter form

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Transfer

• Transfer at the clock edge
• When K1 is high
• n bits wide

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Symbols

• Note memory transfers

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Syntax not Verilog (similar)
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Types of Microoperations

• Transfer have looked at
• Arithmetic
• Logic
• Shift

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Arithmetic

• Basic ops (not multiply, divide)
• R0 ? R1 R2
• Subtraction by 2s complement

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Notation is Shorthand for Hardware

• Consider
• and
• Note overflow
• and carry registers

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Logic Microoperations

• Or notation a little confusing
• shows two ORs

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Shift Microoperations

• Here just the basic one-bit shifts
• Bit falls off the end, zero shifted in

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Multiplexer-Based Transfers

• Consider
• Which can also be expressed as
• Block diagram next

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Multiplexer Block Diagram

• Detailed block diagram next

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Detailed

• Simpler is easier to follow and to derive

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Today

• Looked at two I/O devices
• Keyboard
• VGA display
• Datapaths
• Microoperations
• Next
• Fill out datapaths
• Look at full ALU