Csci 136 Computer Architecture II

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Csci 136 Computer Architecture II A Pipelined
Datapath

• Xiuzhen Cheng
• cheng_at_gwu.edu

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Announcement

• Homework assignment 9, Due time Before class,
  April 05.
• Readings Sections 6.1 6.3
• Problems 6.1-6.4, 6.13-6.14
• Project 3 is due on April 10, 2005

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Topics

• Two pipelined datapath representations
• Single cycle
• Multiple cycle
• Five functional units for pipelined datapath
• Each can be used only within a single pipeline
  stage. Why?
• Comparison of single cycle datapath, multi cycle
  datapath and pipelined datapath
• From one to another
• Sharing of functional unit
• Number of clock cycles
• Clock cycle time
• Temporary registers pass information
• Complexity of control design ( hazards )

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Graphically Representing Pipelines

• multiple-clock-cycle pipeline datagrams
• Can help with answering questions like
• how many cycles does it take to execute this
  code?
• what is the ALU doing during cycle 4?
• use this representation to help understand
  datapaths

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Pipelined Datapath
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Single Cycle Datapath
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Multi Cycle Datapath
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The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Current Topics
• Pipelining is an implementation technique in
  which multiple instructions are overlapped in
  execution

Processor
Input
Control
Memory
Datapath
Output
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Single-Cycle Pipeline Datagram

• What do we need to add to split the datapath into
  stages?

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Pipelined Datapath
64
128
64
97

• how many bits stored in each pipeline register?

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Observations

• 5-stage pipeline
• IF, ID, EX, MEM, WB
• Left-to-right flow of instructions
• Instructions and data move generally from left to
  right
• Two exceptions WB stage and the selection of PC
• May lead to data hazards and control hazards
• Why there is no pipeline register at the end of
  the WB stage?
• Last stage must update either register file, or
  memory, or PC

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Pipelining the Load Instruction
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Clock
2nd lw
3rd lw

• The five independent functional units in the
  pipeline datapath are
• Instruction Memory for the Ifetch stage
• Register Files Read ports (busA and busB) for
  the Reg/Dec stage
• ALU for the Exec stage
• Data Memory for the Mem stage
• Register Files Write port (bus W) for the Wr
  stage

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The Four Stages of R-type
Cycle 1
Cycle 2
Cycle 3
Cycle 4
R-type

• Ifetch Instruction Fetch
• Fetch the instruction from the Instruction Memory
• Reg/Dec Registers Fetch and Instruction Decode
• Exec
• ALU operates on the two register operands
• Wr Write the ALU output back to the register file

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Pipelining the R-type and Load Instruction
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
Oops! We have a problem!
R-type
R-type
Load
R-type
R-type

• We have pipeline conflict or structural hazard
• Two instructions try to write to the register
  file at the same time!
• Only one write port

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Important Observation

• Each functional unit can only be used once per
  instruction
• Each functional unit must be used at the same
  stage for all instructions
• Load uses Register Files Write Port during its
  5th stage
• R-type uses Register Files Write Port during its
  4th stage

• 2 ways to solve this pipeline hazard

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Solution 1 Insert Bubble into the Pipeline
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
Load
R-type
Pipeline
R-type
R-type
Bubble

• Insert a bubble into the pipeline to prevent 2
  writes at the same cycle
• The control logic can be complex
• Lose instruction fetch and issue opportunity
• No instruction is started in Cycle 6!

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Solution 2 Delay R-types Write by One Cycle

• Delay R-types register write by one cycle
• Now R-type instructions also use Reg Files write
  port at Stage 5
• Mem stage is a NOOP stage nothing is being done

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1
2
3
5
Exec
Mem
R-type
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
R-type
R-type
Load
R-type
R-type
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The Four Stages of Store
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Store
Wr

• Ifetch Instruction Fetch
• Fetch the instruction from the Instruction Memory
• Reg/Dec Registers Fetch and Instruction Decode
• Exec Calculate the memory address
• Mem Write the data into the Data Memory

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The Three Stages of Beq
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Mem
Beq
Wr

• Ifetch Instruction Fetch
• Fetch the instruction from the Instruction Memory
• Reg/Dec
• Registers Fetch and Instruction Decode
• Exec
• compares the two register operand,
• select correct branch target address
• latch into PC

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Pipelined Execution of Load Instruction
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Pipelined Execution of Load Instruction
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Pipelined Execution of Load Instruction
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Pipelined Execution of Load Instruction
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Pipelined Execution of Load Instruction
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Pipelined Execution of Store Instruction
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Pipelined Execution of Store Instruction
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Observations from Load and Store

• Pass information needed from an earlier stage to
  a latter stage
• Each logical component of the datapath such as
  IM, Reg read ports, ALU, DM, Reg write port can
  be used only within a single pipeline stage.
  Otherwise, we would have structural hazard
• A bug in the pipelined datapath for load. Can you
  tell?

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Modified Datapath For Basic R-Type, LW/SW, and
BEQ
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Pipelined Execution for Multiple Instructions
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Pipelined Execution for Multiple Instructions
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Pipelined Execution for Multiple Instructions
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Pipelined Execution for Multiple Instructions
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Pipelined Execution for Multiple Instructions
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Pipelined Execution for Multiple Instructions
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Pipelined Datapath Control
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Overview on Datapath Control

• For the subset of instructions under
  consideration, N1.
• ALUOp 00 for Add, 01 for Sub, and 10 for R-type

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Observations

• No write control for all pipeline registers and
  PC since they are updated at every clock cycle.
• To specify the control for the pipeline, set the
  control values during each pipeline stage.
• Control lines can be divided into 5 groups
• IF NONE
• ID NONE
• ALU RegDst, ALUOp, ALUSrc
• MEM Branch, MemRead, MemWrite
• WB MemtoReg, RegWrite
• Group these nine control lines into 3 subsets
• ALUControl, MEMControl, WBControl
• Control signals are generated at ID stage, how to
  pass them to other stages?

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Pass Control Signals

• Extend the pipeline registers to include control
  information

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The Complete Pipelined Datapath
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Example Pipeline Execution

• Show the five instructions going through the
  pipeline lw 10, 20(1) sub 11, 2,
  3 and 12, 4, 5 or 13, 6, 7
• add 14, 8, 9
• Note that these instructions are independent with
  each other!

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Clock1
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Clock2
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Clock3
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Clock4
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Clock5
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Clock6
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Clock7
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Clock8
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Clock9
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Questions?