IO PADS

1
I/O PADS

• In, Out , InOut , Gnd , Vdd,
• Source follower

2
Bidirectional Pad -Digital Component.

• Operates as Pad_in or Pad_out
• EO high gt pad out.
• EO low gt pad in.

3
Pad Layout
DataIn
OE
DataOut
DataInUnBuf
DataInBuf
4
Pad In DC Analysis
DataInB, after one inverter, has less gain than
dataIn
5
Max frequency 100Mhz

• VinBar
• Vin
• Vpad

• Dx 4.11nsec (gt8054nsec)
• Cursers mark position where output exceed 80 of
  max input value

6
Pad out Dc Analysis

• Response similar to dataIn.
• Explanation It has two levels of amplifying, as
  the dataIn node.

7
Max frequency 30Mhz with 10pF capacitor as load

• Vpad
• DataOut

Dx 14.06nsec (gt 801713.6nsec) Cursors mark
position where output exceed 80 of max input
value
8
Sf with no ideal current source

• Function Pad follows Signal, with DC offset.

9
SF Layout
Vss
Vdd
Signal
10
SF behavior (with the pmos as current source)

• Current source values -190 to -150 uA
• 0ltVinlt4 volt, the SF follow the input with 0.85 V
  offset.

3.5V
4 V
11
Lets have a closer look
Vpad Vsignal 0.85 constant when 0 lt Vsignal
lt 4
12
Slew Rate of the SF

• Vsignal
• Vpad
• Vpad-Vsignal

Vsignal ramp from 0 to 5v in 1usec The SF still
follow the step in the range of 0ltVSignallt4volt
13
Pad I/O With ESD
D2
D1

• Two diodes are placed to protect the chip, and
  are normally at reverse charge.
• When signal exceeds 5Vb volts, then D2 is
  forward biased and discharges the excess voltage.
  
• When signal is below Vb, then a similar
  discharging process occurs through D1.

14
PadIOEsd Layout
Diode 2 ? D2 in scehematic
Diode 1 ?D1 in schematic
signal
15
Modeling the Pad

• The modeling was done by attaching a capacitor,
  and a resistor, to the pad. They reperesent the
  capacitance and resistance of three main models
  Human, machine, and package.

To run simulation, an initial voltage was
initialized on the model.
16
Human model.
R1.5kO, C100pF, Initial Voltage 2kV
17
Machine Model.
R25O, C200pF, Initial Voltage 200V
18
Package Model
R1O, C1.5pF, Initial Voltage 2kV