TROY: Track Router with Yielddriven Wire Planning

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TROY Track Router with Yield-driven Wire Planning

• Minsik Cho (thyeros_at_cerc.utexas.edu)
• Hua Xiang (huaxiang_at_us.ibm.com)
• Ruchir Puri (ruchir_at_us.ibm.com)
• David Z. Pan (dpan_at_ece.utexas.edu)
• Dept. of ECE, University of Texas at Austin
• IBM Research, Yorktown

Supported by SRC, IBM and Intel
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Outline

• Introduction
• TROY Algorithm
• Overview and background
• Wire ordering
• Wire sizing/spacing
• Experimental results
• Conclusion and future work

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Track Routing

• Significant Impact of Routing
• Manufacturability
• CMP variation Cho ICCAD06
• CA (Critical area)
• Lithography Mitra DAC05
• Intermediate step between GR and DR
• To speed up DR
• Embed long wires in a panel in each layer
• Accurate information on neighboring wires
• Useful for crosstalk optimization
• Essential for critical area/yield optimization

panel
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Critical Area For Yield
C
A
B

• Random defect can cause open/short defect
• Wire planning for critical area reduction
• Defect size distribution
• Chance of getting larger defect decreases rapidly
  TCAD85
• Concurrent optimization for open/short defect
• Larger wire width for open, but larger spacing
  for short defect
• Limited chip area

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Previous Works

• Track routing
• Track Assignment A Desirable Intermediate Step
  Between Global Routing and Detailed Routing
  Batterywala ICCAD02
• Wire packing A strong formulation of
  crosstalk-aware chip-level track/layer assignment
  with an efficient ILP Kay ISPD00
• Timing- and Crosstalk-Driven Area routing Tseng
  TCAD01
• Timing Driven Track Routing Considering coupling
  Capacitance Wu ASPDAC05
• Critical Area/Yield optimization
• Wire ordering/spacing Bamji DAC96, Bourai
  DATE00, Kuo TCAD94
• Redundant link Kahng ICCAD02
• Wire spreading Allan TSM04, Su ICCAD97
• Drawbacks
• Defect distribution is not considered.
• Trade-off between open and short defect is
  ignored.
• Suboptimal greedy/local optimization

TROY is the first yield-driven track router with
near-optimal trade-off between random defects.
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TROY Strategy
minimize overlapped wirelength between neighbors
by finding min. Hamiltonian path
Integer nonlinear programming
Wire sizing/spacing
optimal wire size/spacing for the entire layer by
SOCP

• Second order conic programming
• Convex programming
• Primal-dual interior point solver
• Near linear time complexity

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Notations

• Wire spacing
• Adjacent wires
• Overlapped wirelength
• Adjacent and overlapped wirelength
• Preferred location for minimum detailed wirelength

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Math for Critical Area
Defect size distribution r 3
Critical are due to open defect
Critical are due to short defect
Probability of failure (POF) for open/short
defects
Approximated POF

• POF is convex function.
• Global optimal can be found, but POF is
  complicated.
• Approximated POF is also convex, but easy enough
  to enable SOCP.

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Yield-Driven Track Routing
Additional POF for open after detailed routing
POF for short
POF for open

• Integer nonlinear programming
• Integer variable for the wire order (which is
  above/below which)
• Key observation
• Objective is convex, which can be further written
  in rotated conic form if the approximated POF is
  adopted.
• If all integer values are given, can be rewritten
  into second order conic programming which is
  efficiently solvable by interior point method.

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Wire Ordering
Solved by finding minimum Hamiltonian path
Initial solution from interval packing
Solved by finding preference-aware minimum
Hamiltonian path
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Wire Ordering
Need to take wires from neighboring panel in to
account
New clique for wire ordering
Order changed
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Wire Spacing

• When wire order is fixed, for each wire
  width/spacing,
• Two auxiliary variables are introduced.
• Two rotated quadratic conic constraints are
  added.
• SOCP is solved for one entire layer.
• Provides globally optimal wire width and spacing

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Experimental Result

• ISPD98 IBM benchmark
• Global routing done by BoxRouter Cho DAC06
• Modified LKH solver for preference-aware minimum
  Hamiltonian path
• MOSEK 4.0 for SOCP
• Intel P4 3.0G with 1G RAM
• Comparison
• Greedy algorithm Tseng TCAD01
• TROY continuous wire width
• TROY.D discrete wire width
• Monte Carlo simulation with 10K defects

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Yield Improvement

• On average 18 reduction in yield loss, up to
  30
• 2.2 improvement loss with discrete wire width

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Runtime Overhead

• Runtime is significantly larger than greedy
  approach.
• FILE I/O, initialization overhead in the solvers.
• But, SOCP is very scalable

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Conclusion

• Track routing is attractive stage to minimize
  critical area for yield enhancement.
• TROY is the first yield-driven track router.
• Wire ordering by preference-aware minimum
  Hamiltonian path
• Wire sizing/spacing by SOCP
• Result is very promising.
• 18 reduction in yield loss due to random defects
• Runtime overhead exists, but TROY is very
  scalable.

Thank you!