Lesson 4: Introduction to PLDs and MAX PLUS II

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Lesson 4 Introduction to PLDs and MAXPLUS II
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Why use a PLD?

• Unlike integrated circuit logic 74xxnn, functions
  can be changed.
• One chip can be programmed by the user with any
  function.
• Conserves design time, space, weight, power.
• Circuit boards with fewer components to assemble.

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PLD types

• PAL programmable array logic
• GAL generic array logic
• EPLD erasable PLD
• CPLD complex PLD
• Have several programmable section that are
  interconnected in a single chip
• FPGA field programmable gate array

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Programming

• Requires special software such as MAXPLUS II
  which includes
• Schematic capture (Graphic Design Files)
• Text-based language such as AHDL (Altera Hardware
  Description Language)
• Industry standard language VHDL (VHSIC Hardware
  Description Language)
• VHSIC very high speed integrated circuit

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Why use MAXPLUS II ?

• Its free software. Anyone can download it from
  Alteras web site.
• It is taken seriously by the industry.

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The PLD Design Cycle

• Design entry
• Simulation
• Fitting
• Programming

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Basics

• When creating a new file, it is standard practice
  to SAVE the file and then SET PROJECT TO CURRENT
  FILE
• Create a separate folder for each new design
  project. Create it on the network drive.
  \username\max2work\projectfolder

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Splash Sheet
Splash Sheet
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Start a new Graphic Design project

• Click on the Create New File icon
• Select Graphic Editor file
• Click OK
• Click the Save icon
• Enter the full path in the File Name textbox
  \max2work\projectfoldername\projectname
• Select .gdf as the automatic extension
• Click OK
• Click the Set Project to Current File icon.

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New File Icon
New File Icon
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New File Dialog Box
Select this option
.gdf
When done.
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Save File Icon
Save File Icon
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Save File Dialog Box
Type in \NewFolder\NewFile
Select your network drive
When done
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If the NewFolder director does not yet exist
Click
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Set Project to Current File
Click this Icon (Nothing seems to happen.)
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Add a symbol
In the workspace, right mouse click to get this
menu
Left mouse click on ENTER SYMBOL
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Specify a symbol
Type in the name of the desired symbol. In this
case and2 will produce a 2 input AND gate
symbol.
When done
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Now you have a symbol !
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Copy the Symbol
Right click on the symbol to get this menu.
Left click on COPY to copy the symbol into
memory.
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Paste a symbol
Move the cursor to where you want to paste the
new instance of the symbol and right click.
Click on Paste
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Now you have a new instance of the symbol
New instance of the same symbol.
A symbol that is SELECTED is in a RED box.
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Selected Symbols

• Can be relocated by dragging them.
• Can be deleted by pressing Delete
• Can be flipped horizontally or vertically
• Can be rotated in 90 degree steps
• And lots more.

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Other symbols you can use immediately
input
output
or3
Later you will learn how to get many other
symbols.
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Browse and enter other symbols
Right click in the workspace to get the dialog box
Look for the prim folder in the maxplus2 folder
The prim folder has lots of symbols you can use
prim
Select a symbol and click OK
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Build a decoder
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Connecting symbols

• Mousedown (hold the right mouse key down) at the
  end of one symbol and drag a line to the end of
  another symbol. Then mouseup.
• The line will progress horizontally until you
  mouseup.
• When you mouseup, the line will go to the
  crosshairs. You can place bends wherever you
  want them.
• Connections to a perpendicular line are
  automatic.

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Assign or Edit Pin Names
Right click on the default pin name.
Left click on Edit Pin Name. This highlights
the pin name.
To highlight the pin name you can also double
click or swipe it.
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Assign and Edit Pin Names
With the pin name highlighted, just begin typing
the new name.
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Compiling Design Entry Files

• Compiling converts the design file to one that
  can be used to program the CPLD.
• Must tell MAXPLUS II what kind of chip you want
  to program.

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Assign a Target Device
Click on Assign
Select Device
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Assign a Target Device
Second, select MAX7000S family
Finally,Select EMP7128SLC84-15
When done
First, uncheck this box
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Compiling
Click the compiler button
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The Compiler Window
To Compile, click on Start
The Compile process generates a Programmer Object
File (.pof file).
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Loading the Program into the CPLD
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Opening a Saved Design File
Start the software and then click on the Open
icon.
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Opening a Saved Design File
Clicking on the Open Icon presents the Open
dialog box.
Second, if necessary, select the folder
Fourth, select the file
First, select the network drive
Third, select the file type
When done
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Hierarchical Design

• Symbols within symbols within symbols
• Allows you to re-use designs in newer designs
• Designs are made in layers or levels so that the
  highest level contains components that are
  themselves complete designs

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Creating the default symbol
Click on File
First, you must have a design to encapsulate into
a default symbol
Select Create Default Symbol
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Using the new symbol
You cant use the symbol in the design that you
used to produce it.
Open another (old or new) Graphic Editor file.
Enter the symbol as you would any other symbol.
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Using the new symbol
If desired, this circuit could be made into a
symbol.
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Text File Design

• More powerful than Graphic Design
• More complicated than Graphic Design
• Uses US Military and IEEE standards
• Language is called VHDL for (Very High Speed
  Integrated Circuit) Hardware Description
  Language.
• To use VHDL you must type a text file.

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VHDL Text File

• The Entity Declaration
• Defines the signals used by the function
• Input names
• Output names
• Name of the function
• The Architechture Body
• Defines how the function works
• How outputs respond to the inputs
• How outputs respond to internal signals

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Whats a VHDL file look like?

• LIBRARY ieee
• USE ieee.std_logic_1164.ALL
• ENTITY maj_vot2 IS
• PORT(
• a, b, c IN STD_LOGIC
• y OUT STD_LOGIC)
• END maj_vot2
• ARCHITECTURE majority OF maj_vot2 IS
• BEGIN
• y
• END majority

Library Clause
Entity
Architecture
This design file is ready to go to the compiler.
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Some of the fine points of the VHDL file
Points to the ieee library
LIBRARY ieee USE ieee.std_logic_1164.ALL
A file that lets the compiler interpret values
given to the variables.
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STD_LOGIC
The only two we will use
The single quote marks are important.
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The Entity
Notice this word
ENTITY maj_vot2 IS PORT( a, b, c
IN STD_LOGIC y OUT STD_LOGIC) END maj_vot2
Notice this semicolon
The design file name appears in the first and
last lines as shown
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The Entity
Always use STD_LOGIC
Open parentheses
ENTITY maj_vot2 IS PORT( a, b, c
IN STD_LOGIC y OUT STD_LOGIC) END maj_vot2
Close parentheses and semicolon
Variable list is comma delimited.
A Port is a connection between the CPLD and the
outside world.
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Architecture
Identifier of entity
Make up an identifier of the logic
ARCHITECTURE majority OF maj_vot2
IS BEGIN y c) END majority
Watch punctuation
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Boolean Expression (function)
y

Use and for AND operator

Use or for OR operator

Use parentheses for Minterms and Maxterms

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Compiling