PseudoRandom Pattern Generator Design forColumnMatching BIST

1
Pseudo-Random Pattern Generator Design
for Column-Matching BIST

• Petr Fier
• Czech Technical University
• Dept. of Computer Science and Engineering

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Outline

• Introduction
• Mixed-Mode Column-Matching BIST
• Weighted-Pattern testing splitter
• Results
• Conclusions

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Introduction

• Discussion on the choice of the pseudorandom
  pattern generator (PRPG) in connection with
  Column-Matching BIST design method
• Target low area overhead of both the PRPG and
  other BIST logic

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Column-Matching BIST

• Pseudorandom patterns are generated by PRPG and
  then modified by a combinational logic into
  deterministic ones (by output decoder)
• For test-per-clock, patterns are applied in
  parallel

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Standard Mixed-ModeColumn-Matching BIST

• Combination of pseudorandom and deterministic
  testing (like bit-fixing, bit-flipping).
• Difference these phases are disjoint
• The pseudorandom phase is run first, and then
  deterministic test is generated for undetected
  faults
• 100 fault coverage assumed

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PRPG Issues Choices

• LFSR
• CA
• Sometimes better, but not much (see DSD05)
• LFSR width is one problem to solve
• PRPG fault coverage is the second problem

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PRPG Issues Choices

• m-bit wide LFSR is needed, in the standard
  approach
• Usually, m goes to thousands
• gt high PRPG area overhead

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Solution 1

• Weighted pattern testing
• (LFSR outputs are AND-ed or OR-ed, to obtain
  weighted outputs)
• Shorter LFSR
• Higher fault coverage
• - Weighting logic overhead

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Solution 2

• Splitter
• (LFSR outputs are distributed to m CUT inputs by
  branching them)
• Shorter LFSR
• - Less fault coverage
• No weighting logic overhead

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One Remark to This Weighted Pattern Testing

• 100 fault coverage is not the aim here
• The aim is minimum area overhead
• ?
• More sophisticated methods, like multiple
  weights, MPLFSR, GURT, etc., are not welcome here

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Weighting Logic Effects
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How to Compute Weights

• Weights are derived from test vectors detecting
  random pattern resistant faults (RPRFs)
• Question How to find them?
• Several pseudorandom vectors are applied to the
  CUT (by fault simulation), undetected faults are
  RPRFs.
• Major question How many vectors?

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How to Compute Weights
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Some Comparisons

• c2670 ISCAS benchmark circuit
• 233 inputs

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Scaling Down the LFSR size

• s13207.1 ISCAS benchmark circuit
• 700 inputs

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Conclusions

• Two (simple) PRPG design methods have been
  investigated weighted pattern testing and
  splitting the LFSR outputs
• Primarily targeted to lower the area overhead
• Seems to be simple, but

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Here are the Buts

• Weighted pattern testing works well. OK.But how
  many vectors should be simulated to obtain RPRFs
  to compute the weights?

Numerous experiments have been performed, every
benchmark circuit behaves differently
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Here are the Buts

• How many weights then? No weights, no weighting
  logic. More decoder logics.
• Too much weights, too much weighting logics.
  Less Decoder logics.

Numerous experiments have been performed. No
clue, unless the final result is computed
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Here are the Buts

• The LFSR width can be scaled. OK.But to what
  extent?

Numerous experiments have been performed. No
clue, unless the final result is computed
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One Last Conclusion
Lots to think about