FMD: Silicon detectors New ideas on electronics

1
FMD Silicon detectorsNew ideas on
electronics
FWD meeting, CERN, 17 September 2002 Børge Svane
Nielsen Niels Bohr Institute

• News from Si detector producers
• New ideas on read-out electronics
• Price update on FE electronics

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FMD ring layout
Full FMD 3 inner rings 2 outer rings
Inner Rin4.2 cm Rout17.2 cm Outer Rin15.4
cm Rout28.4 cm
128
256
20x2x1285120 10x2x2565120
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Ring assembly
Si detector
FEE Hybrid
Support Honeycomb?
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Size limitations
Inner segment
Outer segment
145.81 mm
143.68 mm
150 mm wafer
Hamamatsu active max diameter 133.8 mm Micron
max 140 mm, but may extend beyond in 4
corners ST max 134 mm diameter
? May be forced to some design modifications in 4
corners
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Price quotes
Hamamatsu
design inner segment 51.0 k 3 prototypes
(inner) 11.8 k design outer segment 51.5
k 3 prototypes (outer) 11.8 k production
(100 pc) 154.8 k
280.9 k 420 kCHF
Micron Semiconductors
design inner segment 15.0 k design outer
segment 15.0 k silicon masks
10.0 k 10 prototypes 35.0
k production (100 pc) 100.0 k
175.0 k 408
kCHF mounting bonding 50 k 116 kCHF !!
ST Microelectronics
For 500 ?m thick detectors price indication
600-700 per segment plus some design cost
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FMD electronics
FMD channel count
Tentative FMD cable count
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Inner Si sensor
VA-32 preampshaper
256 strips 2 ? sectors
Connector Multiplexed read-out 256 ch gt 25 ?sec
read-out time
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Hybrid with Viking chips
Connector(s) for power, control, read-out

• Hybrid cards must contain
• VA chips
• Power distribution/regulation
• Gate/strobe distribution
• Read-out control and clock
• Monitoring
• Bias voltage

Other components

• Read-out architecture choice
• 1. Analog signals to shoe-boxes
• (like SSD) long analog cables
• ADC on/near hybrids (like TPC)
• short analog, very long digital cables

VA preampshaper 32 ch
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Reminder VA architecture
32/64/128 input channels
Analog mux out 10 MHz
Strobe from LVL1 trigger
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Analog read-out architecture
Copy Belle or SSD
Disadvantages Long cables with analog signals
need buffer amp Find
space for shoe-boxes
Probably substancial modifications of HALNY
modules DCS separate
architecture
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TPC FEE architecture
http//ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc
/
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ALTRO Layout and Package
2.5 ?m (ST)
Data Memory 1K x 40
Processing Logic
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ALICE TPC READOUT CHIP Principle

• 16-ch signal digitizer and processor
• HCMOS7 0.25 ?m (ST)
• area 64 mm2
• power 16 mW / ch
• prototype delivery Feb 02
• 300 samples fully tested
• delivery of 40,000 chips Dec 02
• cost 5 SFr / ch

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ALTRO Chip ADC Resolution
Integrated ADC better than external version!
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FMD read-out based on ALTRO
Can we use ALTRO as ADC in the FMD read-out,
based on VA preamp-shaper chips ?

• Yes, probably (needs some testing)
• run one VA mux output into one ALTRO input at ?
  10 MHz
• use ALTRO as a pure ADC (forget the processor
  capabilities)
• store event in ALTRO digital memory

Advantages Very short cables with analog
signals ADC and event
buffer directly on FMD detector
Transmit digital data directly to DAQ
We can make a simplified TPC
read-out system DCS and
trigger integral part of system
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TPC read-out architecture
Each TPC Sector is served by 6 Readout Subsystems
COUNTING ROOM
ON DETECTOR
Front-end bus (160 MB / sec)
FEC 128 ch
25
RCU
Data Compr.
DDL - INT
FEC 128 ch
2
BOARD
CTRL
Interface
Controller
Slow-Control
Local
Slow Control (1 Mbit serial link)
FEC 128 ch
1
TTC-RX
Local Slow- Control Serial link
Overall TPC 4356 Front End Cards
216 Readout Control Units
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New FMD read-out architecture
Strongly inspired by TPC read-out, the FMD
read-out could look like this
Each FMD (half)ring is separate Readout Subsystem
VA
COUNTING ROOM
ON DETECTOR
Analog serial link (10 MHz)
Segment 256/512 ch
RCU
ALTRO.
DDL - INT
Segment 256/512 ch
BOARD
CTRL
Interface
Controller
Slow-Control
Local
Slow Control (1 Mbit serial link)
Segment 256/512 ch
TTC-RX
Local Read-out and Slow- Control link
Overall FMD 70 Segments (hybrid cards)
5 or 10 Readout Control Units
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Read-out channel count
We only need 1 ALTRO per ring to stay within 100
?s read-out of TPC But modularity suggests
at least 1 RCU per half ring and by adding
more ALTRO in RCU, we get fast read-out
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Electronics cost
IDEAS
VA modificationprototype 55 k VA production
90 k ? hybrid design
20 k hybrid production
30 k ? test equipment
10 k
205 k 300 kCHF
RCU
board design and tests in house -
where? ALTRO chips 5
k board production (10 pc) 10 k
16 k 24
kCHF design
DAQ
RORC ? other ?
DCS
power supplies ? monitoring ?
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Conclusions
Si strip sensors

• Si strip sensors are squeezed in 4 corners by
  effective wafer size
• ? cut some acceptance?
• Quotations from 2 out of 3 known suppliers
  suggest price ? 400 kCHF
• Need more quotes on mounting bonding could
  be gt 100 kCHF

Electronics

• FE electronics based on VA amplifiers still
  preferred
• BE layout has developed towards a simplified
  version of TPC
• ? proof of principle needed soon
• Price of electronics estimated at 300 kCHF
  (FE) 50 kCHF (BE)