CoE 455 Lab 2 Presentation

1
CoE 455Lab 2 Presentation

• Brad Scheppler
• Kwame Gyang

2
Overview

• Objective Digital Voltmeter
• Overall Design
• Ramp Method
• Software
• Hardware
• Successive Approximation
• Software
• Hardware
• Comparison Software vs. Hardware

3
Objective

• To build a digital voltmeter.
• Two methods
• Ramp Method
• Successive Approximation
• Two Types of Implementation
• Software
• Hardware

4
Overall Design

• The following is the flow chart for the overall
  design of the digital voltmeter.

MC68000 or FPGA outputs guess in digital format
Digital guess is converted to an analog signal.
Guess is compared to the unknown.
Output of the comparator is put through resistive
network
Output of resistive network is put back into the
FPGA.
MC68000 or FPGA uses output of comparator to
computer next guess.
5
Resistor Network

• The following diagram is the resistor network
  used to compare the output of the DAC to an
  unknown voltage.
• Goal was to create a resistor network that input
  5 volts into xio(0) when the comparison was true
  and 0 volts into xio(0) when the comparison was
  false.

5V
Unknown Voltage
120 ohms
75 ohms
Comparator
DAC
Xio(0)
MC6800 or FPGA
6
Delay in the Comparator

• This screen capture shows the delay in the
  comparator.

7
Ramp Method

• Algorithm
• Guesses unknown voltage to be a certain value
  (255 or 5V)
• Compares guess voltage to unknown.
• If less guess is less than unknown then decrement
  guess and compare again.
• Algorithm terminates when guess is just greater
  than unknown.

8
Flow Chart Ramp Method
Step2 Move D0 to DAC
Step1 Initialization Set D0 to 255
Step3 Compare xi0 to 0. If equal to 1 Step5,
else go to Step4
Step4 Decrement D0
Step5 Done, unknown voltage is D0
9
Steps used in Ramp Method

• Initialize D0 to 255
• Insert delay (10 NOPS)
• Write D0 to the input DAC
• Read value at xi0 and Compare to 0
• If equal D0 is the approximately equal to the
  unknown voltage source. Exit loop.
• Else Insert delays (5 NOPS),
• Decrement D0 and start over from 2

10
Operations of Ramp Method Software(Maximum Time)

• 76 clock cycles for one step in ramp method
• Maximum number of steps is 255
• Max time for 1 value 76 255 19380 cycles
  or 2.4225 ms
• Time over 8 values 8 2.4224ms 19.38 ms

11
Operations of Ramp Method Software(Minimum Time)

• 76 clock cycles for one step in ramp method
• Minimum number of steps is 1
• Max time for 1 value 76 1 76 cycles or 9.6
  us
• Time over 8 values 8 9.6 us 76 us

12
Operations of Ramp Method Software(Average Time)

• 76 clock cycles for one step in ramp method
• Maximum number of steps is 128
• Max time for 1 value 76 128 9728 cycles or
  1.216 ms
• Time over 8 values 8 1.216 ms 9.728ms

13
Hardware Implementation of Ramp Method

• Use FSM to
• control and enable an external counter.
• To reset counter to 255
• To assert cntrl_print signal when guess is equal
  to unknown voltage

14
Finite State Machine (Ramp Method)

• RESET set cntr_le 1, out_255 255, cntr_ce
  and cntrl_print 0
• NOP_STATE output signals keep save state. Stay
  here as long as comparator output 0
• LOW cntr_le and cntrl_print 0, cntr_ce 1
• HIGH cntrl_print 1, cntr_ce and cntr_le
  0

LOW
NOP_STATE
HIGH
reset
15
Operation of Ramp Method in Hardware(Maximum
Time)

• Clk 1 Hz
• RESET takes 1 cycle
• NOP_STATE takes about 20 cycles
• LOW state takes anywhere from 1- 256 clock
  cycles.
• HIGH state takes 1 cycle
• Max Time 1202561278 clock cycles 278us

16
Operation of Ramp Method in Hardware(Minimum
Time)

• Clk 1 Hz
• RESET takes 1 cycle
• NOP_STATE takes about 20 cycles
• LOW state takes anywhere from 1- 256 clock
  cycles.
• HIGH state takes 1 cycle
• Minimum Time 1201123 clock cycles 23us

17
Operation of Ramp Method in Hardware(Average
Time)

• Clk 1 Hz
• RESET takes 1 cycle
• NOP_STATE takes about 20 cycles
• LOW state takes anywhere from 1- 256 clock
  cycles.
• HIGH state takes 1 cycle
• Average Time 1201281150 clock cycles
  150us

18
Printing Voltage to Terminal

• Goal is to output a voltage value between 0
  255 as x1y1z1.x2y2z2 volts.
• Algorithm
• Store voltage to be printed in D1
• Initialize register D0 390625
• This value is the step in voltage corresponding
  to adding or subtracting 1 from the guess value
  and obtained by dividing the voltage range by the
  total number of steps or divisions. E.g. (5
  (-5)) / 256 0.0390625.
• Subtract 128 from D1
• The values in D1 between 255 and 128 represent
  voltages between 5V and 0V. Hence the magnitude
  of the number resulting from subtracting 128 from
  D1 is the voltage of the unknown. If the number
  after subtracting is less than 0, then the
  unknown voltage source is a negative voltage, and
  a flag is set by setting register D4 to 1.
• Multiply D3 by D1 to get the REAL voltage which
  is printed to screen

19
Printing to Terminal

• Print Algorithm enters a loop where
• D1 (real voltage) is divided by 10
• Remainder is stored in the upper first half of
  destination register
• Destination register is shifted left by 16 until
  this value occupies the 16 bits from LSB
• This value is temporarily stored in memory
• MOVE.B D0,-(A2)
• Loop returns to step 1 until all values have been
  read.
• Final Stage
• Values read from memory in reverse order and
  written to terminal by calling the OUTCH
  function.
• MOVE.B (A2),D0
• The word volts is printed to screen
• Finally a carriage return and newline is printed
  to screen.

20
Operation Printing

• Total Number of clock cycles used
• 1168 cycles
• Clock frequency 8 MHz
• Takes 146 us to print an answer !

21
Successive Approximation (SA)

• Uses a binary search technique to find the
  unknown voltage.
• Simple example with N3

cmp1
Guess 111
cmp1
111
cmp0
110
Guess 110
cmp0
cmp1
cmp1
Guess 101
101
cmp0
Guess 100
100
cmp0
cmp1
Guess 011
cmp1
011
cmp0
Guess 010
010
cmp0
cmp1
Guess 001
001
cmp0
000
22
Flow Chart for SA

• This flow chart is used in both the software and
  hardware design.

Step1 Initialization
Step 2 Successive Approximation
Step 3 Add to total
Step 4 Compute Average
Step 5 Print Answer
23
Highlight of SA Software Steps

• Step 2 The successive approximation phase of
  the algorithm works as follows
• It places the number 128 into register D0.
• Sends the value in register D0 (128) to the
  address of A0 (which is connected to the DAC)
• We then perform a couple of NOPs so that we
  compensate for the comparators delay.
• We then move the value at address A1 (the
  comparator value) into the register D1.
• We then compare D1 to 0 and if it is not equal
  then we subtract 128 from D0 and if it is equal
  then we do not subtract 128 from D0.
• Repeat steps 1-5 with the value 64 then 32 then
  16 then 8 then 4 then 2 then 1.

24
Operation of SA Software

• 92 clock cycles to test each bit
• 14 clock cycles for the final branch
• Total 848 clock cycles to find 1 value (106us)
• Average over 8 values
• Total 6784 clock cycles
• 994 microseconds to find 1 value

25
Hardware Implementation of SA

• Use a FSM to exert control signals to 8
  registers.
• The 8 registers represent our current guess for
  the voltage.

26
FSM Flow Chart

• Reset set ld71 and d71
• Sn state set resetcmp and ld(n-1)1 and
  d(n-1)1
• Each Nop state represents 22 states, all of which
  do nothing. This allows for the 20us delay from
  the comparator.

S6
S5
S4
S7
Nop7
Nop5
Nop6
nopr
Nop4
reset
S3
S2
S1
S0
print
Nop1
Nop2
Nop3
Nopp
27
Operation of SA Hardware

• Clk 1 Hz
• 10 Nop states, each with 22 states gt 220us
• 8 S-states plus reset and print gt 10us
• Total 230us for 1 value
• Average over 8 values software overhead gt
  1.989ms

28
Maximum Error

• Max error 0.0390625 volts
• Why? b/c 8 bits were used to display value
  between -5V and 5V

29
Conclusion

• Which method is faster?
• successive approximation
• Less comparisons on average