CPE421 MSP430 Review

1
CPE421 MSP430 Review

• (selected excerpts from MSP430 User Guide and
  MSP430F149 Data Sheet)
• March 26, 2007
• Joel Wilder

2
Interrupts Review

• Interrupt priorities determine what interrupt is
  taken when more than one interrupt is pending
  simultaneously.
• Types of interrupts
• System reset
• Non-maskable
• Maskable (The GIE bit in the status register must
  be enabled)

3
Interrupts Review

• Non-maskable interrupts
• An edge on the RST pin (when configured through
  WDT control register)
• An oscillator fault
• Flash access fault

4
Non-maskable Interrupt Handler
5
Maskable Interrupts

• Maskable interrupts are caused by peripherals
  with interrupt capability including the watchdog
  timer overflow in interval-timer mode.
• Each maskable interrupt source can be disabled
  individually by an interrupt enable bit, or all
  maskable interrupts can be disabled by the
  general interrupt enable (GIE) bit in the status
  register (SR).

6
Interrupt Processing

• When an interrupt is requested from a peripheral
  and the peripheral interrupt enable bit and GIE
  bit are set, the interrupt service routine is
  requested.
• Only the individual enable bit must be set for
  (non)-maskable interrupts to be requested.

7
Interrupt Processing

• Interrupt latency is 6 cycles.
• Any currently executing instruction is completed.
• The PC, which points to the next instruction, is
  pushed onto the stack. (return address)
• The SR is pushed onto the stack.
• The interrupt with the highest priority is
  selected if multiple interrupts occurred during
  the last instruction and are pending for service.

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Interrupt Processing

• 5. The interrupt request flag resets
  automatically on single-source flags. Multiple
  source flags remain set for servicing by
  software. (such as port 1 or port 2 interrupts)
• 6. The SR is cleared. This terminates any
  low-power mode. Because the GIE bit is cleared,
  further interrupts are disabled.
• 7. The content of the interrupt vector is loaded
  into the PC the program continues with the
  interrupt service routine at that address.
  (Corresponds to which peripheral caused the
  interrupt)

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Interrupt Processing
Stack
Status register
10
Return from Interrupt

• Takes 5 cycles to execute.
• The SR with all previous settings pops from the
  stack. All previous settings of GIE, CPUOFF, etc.
  are now in effect, regardless of the settings
  used during the interrupt service routine.
• The PC pops from the stack and begins execution
  at the point where it was interrupted.

11
Return from Interrupt
Stack
Status register
12
Interrupt Nesting

• Interrupt nesting is enabled if the GIE bit is
  set inside an interrupt service routine. When
  interrupt nesting is enabled, any interrupt
  occurring during an interrupt service routine
  will interrupt the routine, regardless of the
  interrupt priorities.

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Interrupt Vector Table
The vector contains the 16-bit address of the
appropriate interrupt-handler instruction
sequence.
14
P1 and P2 Interrupts

• Each pin in ports P1 and P2 have interrupt
  capability, configured with the PxIFG, PxIE, and
  PxIES registers. All P1 pins source a single
  interrupt vector, and all P2 pins source a
  different single interrupt vector. The PxIFG
  register can be tested to determine the source of
  a P1 or P2 interrupt (I.e., the signal on which
  pin caused the interrupt).

15
P1 and P2 Interrupts

• Interrupt flag registers are P1IFG and P2IFG.
• All PxIFG interrupt flags request an interrupt
  when their corresponding PxIE bit and the GIE bit
  are set. Each PxIFG flag must be reset with
  software.
• Only transitions cause interrupts Use Interrupt
  Edge Select Registers P1IES, P2IES to select
  whether the PxIFG flag is set on a rising edge or
  falling edge transition.

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P1 and P2 Interrupts

• For example
• Interrupt Enable P1IE
• Specify which external pins can trigger an
  interrupt
• Interrupt Edge Select P1IES
• Whether its a rising or falling edge that causes
  the interrupt
• Interrupt Flag P1IFG
• In ISR, check which pin caused the interrupt and
  implement that specific interrupt handler. I.e.,
  a signal on any one of 8 pins may have caused
  this interrupt. Use an if-statement to determine
  which caused it. Then, clear this flag so that
  subsequent interrupts will be acknowledged.

17
Low-power Modes
Status register
Clock module
SR turns off clocks to put MSP430 into low-power
modes
18
Low-power modes
DCO off
SMCLK off
ACLK off
MCLK off