*-Casting

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-Casting

• ECE 445 Senior Design Lab
• Summer 2005
• Project 3
• Haider Ali, Kent Borecky

2
Introduction

• Idea is to harness the reconfigurable and
  computational ability of the Virtex-II Pro
• Proof-of-concept SoC design
• Allow XUP boards to communicate with each other
  via Ethernet
• Broadcast audio data to other devices

3
Current Technology

• Several consumer audio devices exist with a wide
  range of playback/storage features e.g. iPod
• However, they are dependent on a PC to transfer
  new data
• Recent news from Apple and others to address this
  shortcoming (e.g. XM/Sirrus radio on iPods)

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Project Features

• Implemented on a reconfigurable platform,
  reducing testing and verification costs, in
  addition to allowing rapid bug fixes
• Portability to any other reconfigurable platform
  by vendors like Altera
• Project infrastructure will allow for
  enhancements like replacing Ethernet with
  Wireless connectivity as well as supporting other
  audio standards

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Design Overview

• Input Device
• Digitally sample audio data at 44.1 KHz from
  Line-In using AC97 Audio Codec (18-bit
  resolution)
• Transfer WAVE/PCM data from SRAM
• Network Transfer
• Encode each audio sample into standard Ethernet
  frame and transfer using PHY device
• Output Device
• Output received audio sample back through AC97
  codec on receiving board

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System Design
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AC97 Audio Codec

• LM4550 implements the popular AC97 Audio Codec
  standard (by Intel)
• Provides a higher level of abstraction from the
  designers perspective you are directly dealing
  with audio data
• Tedious because its a serial protocol

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AC97 Frame Structure
From MIT 6.111 Audio Labkit Homepage

• SYNCH signal indicates start of audio frame each
  audio frame carries a single PCM sample (both
  left (slot 3) and right channels (slot 4))
• Can also provide Surround Sound channel data in
  subsequent slots

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Configuring and Using Audio Codec

• Cold Reset Mechanism
• Configuration Data ROM
• Configuration Controller Implementation
• Serialize
• De-Serialize

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Problems/Challenges AC97 Codec

• Invalid Frames
• Problem The Audio Codec expects exactly 256 bit
  frames and if configured improperly, it enters a
  self-diagnose mode
• Solution Cold Reset Mechanism which resets the
  device connected to Push Buttons
• Pops/Clicks
• Problem Our design inadvertently reconfigures
  the codec after a certain time interval
• Solution Added checks to ensure device is only
  configured once or when reset
• Reading Data from SRAM
• Problem Design did not detect size of data on
  SRAM causing the codec to play to non-audio data
  beyond the WAVE file on SRAM
• Solution Read WAVE file header to determine
  actual file size in SRAM
• Endian-ness Mismatch
• Problem WAVE files store PCM samples in Little
  Endian Codec expects Big Endian format
• Solution Swap bytes read from SRAM Wave files

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LXT972 PHY Ethernet Transceiver

• Works on the Physical Layer of the OSI 7-Layer
  Model
• Both a blessing and a curse
• Great for peer-to-peer connectivity dont need
  to adhere to 802.3 standards
• Implemented MAC to create 802.3 frames in order
  to allow data to pass through standard network
  switches
• Switches operate at the Frame Layer and support
  operation at Full-Duplex Mode

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Physical Layer

• Luckily Xilinx defaulted the transceiver to
  Auto-Negotiate at 100 Mbps (Half/Full Duplex)
  through some careful ingenuity i.e. grounding
  pins
• LXT972 supports the Media Independent Interface
  (MII) allows decoupling of physical
  transceivers from the MACs
• Need to configure through the MDIO

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Problems/Challenges PHY Transceiver

• TX/RX Clocking
• Problem Invalid data transferred even in a
  peer-to-peer setup
• Solution Careful study of PHY TX/RX timing
  diagram revealed that TX is falling-edge clocked
  and RX is rising edge
• Similar clocking issues encountered when
  utilizing the MDIO for PHY configuration

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MAC Frame Format
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MAC Implementation
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Tested Start of Frame

• According to standard, preamble is A.B
• Through testing, the start of frame is 5.D

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Length/Type Field

• Indicates length of data for values smaller than
  the maximum frame size
• Indicates type of frame for values greater than
  the maximum frame size

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Length/Type Testing

• Winpcap allows the sending of arbitrary frames
• Sent an arbitrary frame with the length to a
  obviously incorrect value
• The switch forwarded the packet

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802.3 FCS

• Generated using the following polynomial
  

• First 32 bits are complemented of the input data
• Result is complemented
• Most significant bit is transmitted first

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FCS Testing

• Used Xilinx 802.3 CRC Application Note to
  generate FCS
• Used perl module DigestCRC to compare against
• Sent test frames from another computer using
  Winpcap and captured resulting frames
• Tried various bit orderings, but no matches
  between any of these

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FCS Testing Continued

• Xilinx implementation has generates CRC from bit
  reversed inputs
• http//www.easics.be/webtools/crctool also
  provides a CRC generator. It does not reverse
  the bit inputs
• Neither version seemed to agree with CRCs
  generated by computer ethernet card

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General Frame Testing

• As mentioned earlier, sent arbitrary frames using
  Winpcap
• Set destination to FFFFFFFFFFFF
• Set source to 010101010101
• Sometimes the source address received would show
  as 1111110111
• The computer can send frames that seem to be wrong

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Frame Testing

• Tried capturing frames sent from the project on
  the computer using Ethereal
• No packets successfully captured
• If the packet appears damaged to the ethernet
  card, it will not even pass it to the software

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Problems/Challenges MAC

• Invalid CRC
• Problem Switch drops frames sent from XUP board
• Solution Couldnt isolate the problem with the
  CRC generation standard software CRC different
  from Ethernet CRC, so you cant even hardcode it
  for a given data
• Preamble Ambiguity
• 0x5AB vs 0xAD
• Bit Ordering
• Ethernet frames require all data except CRC to be
  transmitted LSB first CRC is transmitted MSB
  first

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PS/2 Keyboard and XVGA

• Intended to utilize to embed data about current
  audio stream into broadcasted Ethernet frames
• Standard device-to-host communication protocol
  used to interface to keyboard
• Microcontroller onboard keyboards send data in
  frames of 11-bits (start bit, 8-bit data, parity
  and stop bits) 8-bit data is the pressed keys
  scancode
• Scancodes translated to corresponding ASCII values

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XVGA Timing Generation

• 640 x 480 resolution (24-bit color)
• Timing generator drives the VGA PIXEL_CLK,
  HSYNCH, VSYNCH and BLANK signals
• Counters based off of current HSYNCH and VSYNCH
  define current position on screen

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XVGA Timing Generator Horizontal Synch
Controller
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Character Pixel Generation

• No onboard character palettes had to generate
  character pixel data ourselves
• Used ASCII art to generate 8 x 8 pixel
  representation for characters
• Stored on a ROM array and synthesized
• Requires separate ASCII - gt Character ROM Address
  mapping
• So to display typed characters from keyboard
• Scancode -gt ASCII -gt Character ROM Address

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Character Pixel Generation 2
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Problems/Challenges Character Pixel Generation

• Non-static character display location
• Problem Characters would appear to be moving
  upwards
• Solution Because the design deals with
  interfacing directly with video signals, it is
  necessary that the characters are re-drawn at the
  same pixel location each time
• Drawing Pixels
• Because of lack of any video memory, each
  character in a sentence needs to be drawn
  row-major order across all characters.

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Simulation and Testing

• Without libraries to model external devices
  (Ethernet Transceiver, Audio Codec), difficult to
  accurately simulate their behavior
• Successfully tested and verified designs not
  directly related to external chips using ModelSim
  Simulator
• Interfacing hardware simulated by hard-coding the
  expected input/outputs from external device
• Synthesized designs using Mentor Graphics
  Precision Synthesis Tool verified RTL generated
  by it with original designs for correctness

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Functional Tests

• Successful communication across two boards
• Local/Remote simultaneous playback
• Multiple types of input data utilized i.e.
  hard-rock, jazz, and spoken words to determine
  any degradation in playback
• With very loud music (e.g. trance), remote
  playback is at times noisy (likely due to the
  fact that the codec is set to output audio with
  gain)
• SRAM/Line-In Input sources
• Keyboard/VGA operational input data included
  all alphanumeric keyboard characters

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Spectral Analysis

• Recorded at same sample rate
• Note that the peaks match
• Magnitudes different due to different volumes
  throughout process

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Phantom of Opera (Trance Mix)44.1 KHz, 16-bit
Stereo (24 s)

• Result

• Original

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Windows Startup Sound (22 KHz, 16-bit Stereo 3 s)
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Bandwidth Analysis Ethernet Audio Codec

• At 100 Mbps (Full Duplex), the LXT972 operates at
  25 MHz (40 ns)
• The Audio Codec runs at 12.5 MHz out of the 256
  bit frames, only 36 bits is audio data
• A typical Ethernet frame would thus be 100 bits
  (64 preamble bits 36 data) 10040 ns 4000
  ns to transfer a audio sample
• However, you cant playback the sample until 216
  clock cycles 17000 ns this is the inherent
  delay within the codec
• Provides ample time to transfer data across can
  transfer other data (video/data in that time)
• In fact 10 Mbps would work also (cutting it close)

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Performance Requirement Latency Test

• As shown in the bandwidth analysis and spectral
  analysis of original and transferred audio
  samples, the original performance requirement was
  met
• Playback on remote side is real time and
  synchronized with local playback
• No noise in remote playback
• If the MAC layer was functional, the bandwidth
  would still be sufficient

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Area Results

• Resource Used Avail
  Utilization
• -----------------------------------------------
• IOs 63 556 11.33
• Global Buffers 6 16 37.50
• Function Generators 921 27392 3.36
• CLB Slices 461 13696 3.37
• Dffs or Latches 695 29060 2.39

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Final Thoughts

• Improvement Get full network connectivity
  through networking switch!
• Improvement Integrate A/V/Data transfer
• Difficult to simulate/debug external devices -
  logic analyzer is helpful but limited to
  available debug pins
• Utilizing common standards (e.g. 802.3) requires
  a sound understanding of protocol and reference
  designs

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Acknowledgments

• Prof Nick Carter (for lab/equipment access)
• Prof Gary Swenson
• Alex Spektor

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Questions?