Lab3 Tutorial using StateCAD

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Lab3Tutorial using StateCAD
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Objective

• This tutorial will give you exposure to using
  StateCAD and VHDL
• Using HDL Bencher and Modelsim for simulating the
  functional design
• This tutorial shows you how to create, using
  StateCAD and VHDL, a simple sequence generator

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Sequence Generator State Table
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Sequence Generator State Diagram
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Create a New Project
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Enter a Name and Location for the Project
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Select the Device and Design Flow for the Project
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Create a New Source
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Select State Diagram and Enter File Name
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New Source Information
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New Source Information
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Next Step
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Finish
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Create a Blank StateCAD
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State Machine Wizard Draw State Machines
Draw State Machines
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Select the Appearance of the State Machine
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Reset the State Machine
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Setup Transitions
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Placed Template State Diagram
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Edit Conditions in the transition arrow
State0?State1
Left-Click
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Output Wizard
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Enter Constraint Value
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Completed Transition
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Modified State Diagram
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Insert a New Transition
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Enter Constraint Value
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Left-Click
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(No Transcript)
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State2?State1
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Left-Click
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Final State Diagram
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Generate HDL
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Optimize Outputs for Speed
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Result Windows
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StateCAD HDL
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Create Test Bench (State Bench)
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State Bench
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Reset
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Input CLK
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Review Sequence Generator State Table
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Summary Sequence Generator State Table

• M0, then
• State 0?2?1?3?0
• M1, then
• State 0?1 ?0 ,
• State 2?0, and State 3?0.

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Check M0 Then DOUT 0,2,1,3(State 0,2,1,3)
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Check M1 Then DOUT 0, 1(State 0,1)
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Check M1 Then State2? State0 and State3?State0
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Questions and Answers