BYU Research and CHREC

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BYU Research and CHREC

• Dr. Brent Nelson Dr. Michael Wirthlin
• Configurable Computing Laboratory
• Dept. of Electrical and Computer Engineering
• Brigham Young University

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Brigham Young University

• Large private university (33,000 students)
• Sponsored by The Church of Jesus Christ of
  Latter-Day Saints (LDS)
• Provo, Utah (45 miles south of Salt Lake City)

Department of Electrical and Computer Engineering
http//www.ee.byu.edu

• 25 Faculty
• Research Areas
• Configurable Computing
• Signal Processing Communications
• Robotics/UAVs
• Machine/Computer Vision
• Electromagnetics
• Microelectronics

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Configurable Computing Laboratory
Ill configure you!

• Established in 1993
• Faculty
• Brent Nelson
• Michael Wirthlin
• Brad Hutchings
• Historical Focus Areas
• Configurable Computing Machines
• Runtime reconfiguration, partial reconfiguration
• Debugging, checkpointing, context switching,
  remote access
• CAD for CCMs
• JHDL Java-based design tools
• Application-specific compilers
• High-Level Synthesis
• HPEC applications
• RADAR, SONAR, target tracking,digital comm,
  high-perf networking
• Arithmetic floating point, finite field mult,
  constant coeff mult

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HPEC-RC

• Complementary to HPC
• Slightly different issues/priorities
• Power, reliability, custom I/O, custom
  architectures
• Nonstandard
• Operating systems
• Development/debug/deployment environments
• Size, weight, power, environmental constraints

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Radiation and Fault Tolerance

• Description
• Increasing use of Reconfigurable Computing in
  space
• Increase understanding of SEU effects
• Demonstrate novel mitigation techniques
• Create automated reliability tools
• Investigate and validate new high risk techniques
  for improving design reliability
• Frequent TMR voting
• Integrated detection/correction
• Timing aware TMR
• Leverage BYU SEU tools
• Fault injection and simulation tool suite
• EDIF netlisting tools
• Partial TMR tools
• Design analysis tools
• XRTC Xilinx Radiation Test Consortium

• Tasks
• Review existing reliability techniques for ASICs
  and evaluate for FPGA adaptation
• Create continuous time reliability models for
  common FPGA mitigation techniques
• Implement and demonstrate dynamic testing
  environment for new architectures
• Demonstrate a variety of dynamic radiation tests
  and test approaches

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Compilation and Synthesis for RC

• Description
• HPC and HPEC RC design tools
• Two-level Compilation System
• High-Level Parallelizing compilers
• High-level, high leverage optimizations
• Loop unrolling, data organization
• Low-Level Hardware synthesis
• Low-level optimizations
• Module selection, scheduling, pipelining (crucial
  for FPGA performance)
• Collaboration between levels architectural
  exploration
• Leverage previous BYU work on pipelined synthesis
• Initial Focus
• Pipelined synthesis techniques
• Synthesis/compilation tool interface

• Tasks
• Identify computationally efficient architectural
  exploration strategies
• Benchmark suites
• Create circuit module library
• Benchmarking, inter-operability, productivity,
  usability studies
• Develop synthesis interface to higher level
  compilation tools

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HPEC Run-Time System and Software

• Description
• Embedded CCMs ? system support
• Operating system support
• Debug techniques and tools
• Run-time reconfiguration control
• Standard communication protocols
• Benefits
• Ease system design
• Ease verification
• Simplify reuse (HW/SW)
• Reusable components
• Approach
• Toolbox
• APIs
• Reference designs

Checkpointing
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Debug Circuitry Synthesis

• Tasks
• Operating system support (emb. Linux)
• Debug and verification support
• Run-time reconfiguration management
• Time-sharing and checkpointing
• Communications and protocols

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HPEC Architectures and Applications

• Description
• HPEC-RC Hybrid/Specialized System Architectures
• PSOCs CPUs RC fabric
• V2-Pro/V4/V5, µBlaze, NIOS
• Networks-on-Chip
• Mixed Architectures
• GPUs, RAW, Cell, Trips FPGAs
• Custom memory architectures
• Applications
• Signal processing/digital comm
• MIMO, SDR, RADAR, SONAR
• Real-time robotic vision
• Sensor networks

• Tasks
• Architectures development
• Applications mapping techniques
• Development testbeds
• Reusable/parameterizable modules
• Arithmetic
• Bit-precision modelling/analysis

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BYU/CHREC Schedule

• Planning proposal approved by NSF (last week)
• Planning meeting March/April 2006?
• Final proposal May