UTCS

1
Lecture 12 Pipelining Hazards and Performance

• Last Time
• Pipelining overview, hazards
• Today
• Hazards continued
• Pipeline performance analysis
• Performance modeling

2
Types of Data Hazards

• RAW (read after write)
• only hazard for fixed pipelines
• later instruction must read after earlier
  instruction writes
• WAW (write after write)
• variable-length pipeline
• later instruction must write after earlier
  instruction writes
• WAR (write after read)
• pipelines with late read
• later instruction must write after earlier
  instruction reads

F
R
1
2
3
4
W
F
R
1
2
3
4
R
5
W
3
Control Hazards
Cycle
F
R
X
M
W
Destination Available Here
F
R
X
M
W
Instruction
Need Destination Here
JR R25 ... XX ADD ...
4
Resolving Hazards Pipeline Stalls

• Can resolve any type of hazard
• data, control, or structural
• Detect the hazard
• What is the logic to detect the hazard?
• Freeze the pipeline up to the dependent stage
  until the hazard is resolved
• Pipeline interlock
• Turn off clock to latches for earlier stages

5
Example Pipeline Stall (Diagram)
Cycle
F
R
X
M
W
Write Data to R1 Here
F
R
X
M
W
Bubble
Instruction
Read from R1 Here
ADD R1, R2, R3 ADD R4, R1, R5
Question Why is it a 2-cycle bubble and not a
3-cycle bubble?
6
Reducing/Eliminating Hazards

• Structural hazards
• Better scheduling of RTL (use reservation table)
  to minimize conflicts
• Provide more hardware
• Control hazards
• Compute branch target more quickly
• Predication to eliminate branches
• Branch delay slot
• Branch prediction (another approach EV6 line
  predictor)
• Data hazards
• Forwarding/bypassing (RAW hazards)
• Better register allocation to reduce WAW/WAR
  hazards
• Hardware register renaming to eliminate it

7
Resolving Data Hazards Bypass (Forwarding)

• If data is available elsewhere in the pipeline,
  there is no need to stall
• Detect condition
• Bypass (or forward) data directly to the
  consuming pipeline stage
• Bypass eliminates stalls for single-cycle
  operations
• reduces longest stall to N-1 cycles for N-cycle
  operations
• mul r3, r2, r1 (3 cycles)
• add r4, r3, r2 (1 cycle)

8
Simple Pipeline with Bypass Multiplexers
IP
IP
4
RW
A
IR
Reg File
I-Mem
D-Mem
C
E
A
DO
A
DO
B
D
DI
IR
IR
IR
9
Data Hazards With Bypassing
Cycle
ADD R1, R2, R3 ADD R4, R1, R5SUB R5, R1,
R6 XOR R7, R8, R1
F
R
X
M
W
R1 computed
R1 used
F
R
X
M
W
ADD
Instruction
F
R
X
M
W
SUB
F
R
X
M
W
XOR
10
Partial bypasses
Cycle
ADD R1, R2, R3 BUBBLE ADD R4, R1, R5SUB R5, R1,
R6 XOR R7, R8, R1
F
R
X
M
W
R1 computed
R1 used
F
R
X
M
W
ADD
Instruction
F
R
X
M
W
SUB
F
R
X
M
W
XOR
What is CPI for above code sequence? How many
cycles?
11
Data Hazards With Bypassing
Cycle
ADD R1, R2, R3 ADD R4, R1, R5SUB R5, R1,
R6 XOR R7, R8, R1
F
R
X
M
W
R1 computed
R1 used
F
R
X
M
W
ADD
Instruction
F
R
X
M
W
SUB
F
R
X
M
W
XOR
12
Summary

• Pipelining principles
• Hazards
• Hazard prevention/reduction
• Next time
• Memory systems