Lecture 23: DRAM Driving large capacitances

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Lecture 23 DRAM Driving large capacitances

• EECS 312
• Reading 10.3.3, 8.2.3, 8.5 (text)

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Lecture Overview

• Midterm 2 review
• Finish discussion of memories
• Chip packaging overview
• Driving large loads

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Midterm 2
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Packaging
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Bonding Techniques
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Flip-Chip Bonding
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Package Types
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Package Parameters
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Driving Large Capacitances
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Using Cascaded Buffers
X CL/Cin u tapering factor
This ignores self-loading (junction capacitance
of driving stage) derivation on page 450 of text
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tp as a function of u and x
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Impact of Cascading Buffers
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Output Driver Design
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How to Design Large Transistors
We dont want a long poly run resistive and
large parasitics Place multiple narrower devices
in parallel (with same gate signal)
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Tristate Buffers
Useful for signals with multiple drivers 2nd
implementation is better in some cases b/c no
series connected devices in output stage
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Lecture Summary

• Chips must be put in a package to interface with
  other devices
• Sending signals off-chip requires a lot of
  driving capability
• Driving large loads is best done using cascaded
  buffers with tapering factor of e