Asynchronous Transient Resilient Links for NoC

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Asynchronous Transient Resilient Links for NoC

• Simon Ogg, University of Southampton
• Bashir Al-Hashimi, University of Southampton
• Alex Yakovlev, Newcastle University

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Outline of Talk

• Motivation
• Related Work
• Proposed Coding Technique
• Circuit Implementation
• Experimental Results
• Concluding Remarks

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Motivation

• Network-on-Chip effective communication for
  multiprocessor SoC
• Large number of Interconnect and Switches
• Asynchronous Links
• Simplify Clocking and Reduce Power
• Standard (Dual-Rail, 1 of 4, etc) coding
  susceptible to transients
• Coding gives resilience to Transient Errors

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Related Work

• Dual Rail
• 2 transitions 2 wires per bit
• LEDR, 1-of-4 (Dean91, Bainbridge01)
• 1 transition 2 wires per bit
• S-C Green Codes (Po-Tsang08)
• 3.75 wires per bit, Resilient to Transients
• M-Rail Phase Encoding (DAlessandro06)
• lt1 wire per bit when bits gt4, Resilient to Trans.

Proposed Coding ?1 transition ?2 wires per bit,
Resilience to Trans.
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Proposed Coding

• Uses 2 wires per bit, plus 2 wires reference
• Data is transmitted as Symbols
• Ref. increments in Gray code 00,01,11,10
• Symbols are in-phase or 180?-phase wrt Ref.

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State Diagram of Coding

• In-phase plane, data 0
• 180?-phase plane, Data 1

REF-SYM
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Example of 4 bit wide data
DATA 0000
DATA 0011
DATA 1111
DATA 1010
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Link Overview

• 1 x Reference Transmit (TX) and Receive (RX)
• 2 Wires per link
• n x Data Transmit and Receive
• 2 Wires per bit

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Connectivity

• Several DATA TX and RX
• 1 REF TX and RX
• Valid signals gated together

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TX REF and RX REF modules

• TX REF increments in Gray code on VALID
• RX REF says when Ref has incremented
• REFINC supplied to RX DATA module

TX REF
RX REF
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TX DATA module

• Takes Ref. and generates data symbol
• Data symbol in-phase or 180?-phase
• Data Symbol latched when Ref. changes

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RX DATA module

• Says when symbol is valid (in-phase or
  180?-phase)
• Generates data and valid signals

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Experimental Results

• Transistor Level Sim. (SpectreVerilog)
• Example waveforms
• Clean waveform
• 1 symbol wire with transients
• 2 symbol wires with transients
• When can it fail?
• Explanation and example
• Area Power

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Clean waveform
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1 Symbol wire with Transient
DATA out Not corrupted
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2 symbol wires with Transient
Transients on both Symbol wires
DATA Not corrupted
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When can it fail?

• Not 100 Resilient to Transients!
• Affected by Transient width
• and Flip-flop setup time in RX DATA module

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Transient Hits within a Symbol Period
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Waveform Corrupted
???
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Area (µm2)
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Average Power (µW)
Static power obtained by running simulation with
no clock or stimulus average(VI) at power input
node
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Comparison to other Asynch. code
where n number of bits and (w-1)! lt 2n lt w!
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Concluding Remarks

• Novel Coding for Asynchronous Links
• Resilient to Transients
• Similar No. of Wire per bit as Dual-Rail, 1-of-4
• Similar No. of Transition as LEDR
• Future Work
• Circuit Module Optimization
• Wire Buffering for long links

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End of Presentation

• Thank you for listening
• Questions?

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Unused Slides

• Unused Slides Placed Here
• Might be interesting to show if any questions
• A proposed wire buffer circuit
• Comparison to M-Rail Phase encoding (area)
• Equation to estimate corruption of data
• Waveform with transients on REF

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Proposed Wire Buffer

• Latches symbol and ref when matched
• Shaded area replicated n times and gated together

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Comparison to M-Rail Phase enc.
Alex, M-Rail Phase encoding goes a bit mental
when the number of bits is greater than 4, talked
to Enzo about it and he said it was a fair
comparison, had to work it out by hand and
estimate size since no real open loop way to get
gates for matrix encoder and decoder.
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P. Corruption within a symbol Period

• How to calculate the probability of corruption on
  the link when transient hits within a symbol
  period.

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Transients on REF