Designing of a D FlipFlop Final Project ECE 491

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Designing of a D Flip-FlopFinal ProjectECE 491
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Objectives

• To familiarize with the function of the D flip-
  flop and it's operation.
• To Draw the schematic and the layout with clocked
  input
• Perform DRC check and generate LVS
• To do the simulation and observed the output
  waveforms
• To Vary the output load(1pf to 5pf) and observed
  outputs

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D Flip Flop (Specification)

• A signal input and a clock signal is used
• AMI-0.6micron process is used
• Wp7.5 u, Wn 3.0 u, LnLp0.6u
• Pre and Post-layout simulations using spectra
• Rise time, Fall time and propagation delay
  increase for the loading effects

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Why DFF

• Preferred type for integrated circuit
  applications (DFF)
• S-R flip flop has indeterminate state when both
  inputs are high
• The JKFF simplifies the RSFF truth table but
  keeps two inputs.

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Symbol
CLK
Q
DFF
D
QB
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Layout
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Schematics
Q
QB
Inverter
Nor
And
And
Nor
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INVERTER
NAND
NOR
AND
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Results
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Delay
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Without load
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Loading Effect
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Negative Edged Trigger