Fast waveform digitization with the DRS chip

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Fast waveform digitization with the DRS chip

• Stefan Ritt
• Paul Scherrer Institute, Switzerland

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The MEG Experiment at PSI

• Needed
• Pile-up rejection (BG from 108 µ decays in
  unsegmented calorimeter)
• ADC dynamic range of 12 bit
• TDC resolution of 40 ps
• Analog pipeline (L1 trigger) 300ns
• 3000 channels

Goal m ? eg at 10-13
2 GS 12 Bit 100 /Chn
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Domino Sampling Chip Principle
0.2-2 ns
Inverter Domino ring chain
IN
Waveform stored
Out
FADC 33 MHz
Clock
Shift Register
Time stretcher GHz ? MHz
Keep Domino wave running in a circular fashion
and stop by trigger ? Domino Ring Sampler (DRS)
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The DRS3 Chip
domino wave

• Design Properties
• 12 channels at 1024 bins
• Cascadable 6x2k, , 1x12k bins
• Sampling speed 10 MHz 5 GHz
• Readout speed 33 MHz
• ROI readout (3 ms for 100 bins)
• Fabricated in 0.25 mm 1P5M MMC process (UMC), 5 x
  5 mm2
• Radiation Hard (CMS Pixel library, R.
  Horisberger)
• Power consumption 50 mW _at_ 2 GHz
• Packaged chip costs
• 35 / chn. (MPW run)
• 3 / chn. (SPW run)

8 inputs
MUX
shift register
Reference clock
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PLL Stabilization

• Temperature coefficient 500ps / ºC
• Jitter after PLL stabilization 200ps / turn
• Improved timing with clock reference channel
  lt100ps

Vspeed
PLL
R. Paoletti, N. Turini, R. Pegna MAGIC
collaboration
External Common Reference Clock (1-4 MHz)
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Linearity and Noise

• Careful design gave linearity 0.1V 1.1Vbetter
  0.5 mV, Tc 50 ppm
• Fixed pattern noise 6 mV (RMS)
• Noise after offset correction (in FPGA code
  during readout) 0.25 mV (RMS) ? 12 bit SNR
• Bandwidth 450 MHz, to beimproved with small
  design change for mass production

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VPC USB boards
USB interfaceboard
DRS3
32 channels input
14-bit flash ADCAD9248
DRS2
PSI general purposeVME board with 2 PPC cores
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Comparison with other chips
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MEG with DRS2

• Drift chamber anode cathode signals _at_ 500 MHz
• Moving baseline
• 50 ns pile-up rejection
• Cluster density ? particle ID

hits
Virtualoscilloscope
Moving average baseline
Crosstalk removal by subtracting empty channel
Template fit
Final noise level 0.32 mV (bin), 0.07 mV
(baseline)
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Real-time aspects

• How to get rid again of the waveform data?

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Managing the waveform data

• 3000 Channels _at_ 100 Hz _at_ 1024 bins _at_ 24 bit 880
  MB/sec
• All data needs calibration
• Need extensive data compression
• Event rate can be improved if compression moves
  upstream

Optimize implementation
MIDAS DAQ
GbitEthernet 100 MB/s
Front-end PC
Back-end PC
DRS
FPGA
PPC
Fiber 84 MB/s
PPC
CPU
CPU
CPU
CPU
VME
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Compression algorithms in FPGA

• Zero suppression hit if max. value gt average
  3 x s
• Readout window start / width in respect to
  trigger
• Pile-up flag Zero-crossings of first derivation
• Re-binning 41, 81, 161
• ADC Numerical integral of hit over baseline
• TDC Only simple threshold (usable to recognize
  accidentals) and time-over-threshold
• Spline calibration
• Waveform fitting

4 ns bins
0.5 ns bins
Must be implemented in PC
Not feasiblein FPGA
TOT
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DAQ cluster

clock start stop sync
pE5 area
cave
Ancillary system
Trigger
Front-End PCs
PC (Linux)
3 crates
Ready
20 MHz clock
Gigabit Ethernet
Event builder
PC (Linux)
PC (Linux)
Trigger
PC (Linux)
PC (Linux)
On-line farm
storage
6 crates
9 VME creates
11 dual-Xenon PCs with hyper-threading
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Event rate before MT

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Multi-threading model
Calibration Thread
Zero-copy ring buffers
VME
Round-Robin distribution
Calibration Thread
VME Transfer Thread
Collector Thread
Calibration Thread
Network
Ring buffer functionsin MIDAS rb_create() rb_get
_wp() rb_increment_wp() rb_get_rp() rb_increment_r
p()
Calibration Thread
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Event rate with 4 threads

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Conclusions

• Waveform digitizing with DRS chip opens new
  exiting possibilities for pile-up recognition and
  pulse-shape discrimination
• This technology can completely eliminate the
  needs for traditional ADCs and TDCs at attractive
  costs
• Switching from ADC/TDC data to waveforms
  increases the demand for computing power and
  storage dramatically and requires new strategies
  for data reduction
• Effective multithreading will be the future in RT
  computing