Bus Serialization for Reducing Power Consumption

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Bus Serialization for Reducing Power Consumption

• 2004/2/18
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Objective

• On-chip bus power consumption is an important
  issue on VLSI design
• Bus serialization for reducing bus power
  consumption
• Quantitative analysis of the effect

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Outline

• Proposition
• Bus Serialization
• Evaluation
• Results and Considerations
• Conclusion
• Future Works

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Proposition
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Concept

• Bus serialization
• Serialized bus replaces conventional bus
• Constraints
• The same area as conventional bus
• The same throughput
• Higher frequency

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Bus Serialization
Bus Serialization (Degree 2)
Bus Frequency f 2
Bus Frequency f
Conventional Bus
Serialized Bus

• Bus serialization decreases the number of wires

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Power Reduction

• The number of wires decreases
• Wire pitch increases in the same area
• Capacitance between wires decreases
• Power consumption decreases

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Evaluation
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Condition

• Bus Specification
• Bus width 64bit
• Degree of Serialization 2
• Wire Configurations (width, height, etc)
• From International Technology Roadmap for
  Semiconductor 2002
• Bit pattern
• Address bus and data bus between processor core
  and L1 cache
• SPECint95 benchmark

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Bus Capacitance
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Power Reduction
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Why Power Increases in Address?
Conventional Bus
Serialized Bus
1001 1001
10 01 10 01
Transition0
Transition3 (0 ? 1)

• Power is consumed when signal transits
• If previous bit pattern is equal to the next
  pattern, serialized bus consumes extra power

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Differential Data Transfer (DDT)
Normal
DDT
Bit Pattern

• Transfer the difference between present data and
  previous data

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Power Reduction (DDT)
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Comparison
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Conclusion and Future Works
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Conclusion

• Normal serialized bus is proper to data bus
• Serialized bus with DDT is proper to address bus
• Bus serialization technique decrease power
  consumption to 70 of conventional in 45nm
  process
• As gate length shrinks, Bus serialization becomes
  more effective

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Future Works

• Full processor model
• Chip multi processor
• Between L1 cache and L2 cache
• Additional costs of DDT
• Additional circuits and delay