Memory Addressing

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Memory Addressing

• NRL File system team
• Lim Donghyouk
• (Dept of Computer Science, KAIST)

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Contents

• Memory Addresses
• Segmentation in Hardware
• Segmentation in Linux
• Paging in Hardware
• Paging in Linux

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Memory Addresses

• Logical Address
• X86 architecture
• A segment and an offset
• Linear Address
• Virtual address
• 32 bit unsigned integer, hexadecimal up to 4GB
• Physical address
• Used to address memory cells in memory chips
• 32 bit unsigned integer
• Address Translation
• Segmentation unit logical to linear
• Paging unit linear to physical

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Segmentation in hardware

• Segmentation Register
• Segment selector(indentifier) 16 bit, offset
  32bit
• Six segmentation Registers for segment
  selection
• cs code segment, ss stack segment, ds data
  segment
• es, fs, gs general purpose
• CPL(current privilege level) 0 kernel mode, 3
  user mode
• Segment descriptor
• Global descriptor table vs Local descriptor table
• Represented by 8byte descriptor
• Base field linear address of first byte
• Granularity flag if it is set, size in 4Kbyte
• System flag system segment that stores kernel
  data structure
• Type field segment type and access right
• DPL Descriptor privilege level
• Segment-present flag Is it in main memory?

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Segmentation in hardware

• Segment selector
• Index 13 bit index
• TI(table indicator) in GDT or LDT
• RPL (Requestor Privilege Level)
• Segmentation unit
• Translate a logical address into a linear address
• Examine TI field find descriptor table
• Computes address of the segment descriptor use
  index field
• Add offset to base field of segment descriptor

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Segmentation in Linux

• Linux uses segmentation in very limited way.
• Segmentation and paging are redundant
• Paging is simpler for memory management
• LDT are not used by the kernel
• Portablity
• Segments used by linux
• Kernel code data segment
• User code data segment sharing by all
  processes
• Task State Segment for each processor
• default Local Descriptor table
• 4 segments for APM

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Paging in hardware

• Regular paging
• Page, Page frame linear vs physical
• Page table map linear to physical address
• Linear address directory(10), table(10),
  offset(12)
• In x86 page size 4KB, two level scheme
• Level scheme reduce amount of RAM for process
  Page Table
• Directory (in cr3 register) -gt table -gt page
• Page Table entry
• Present flag, Accessed flag, dirty flag, R/W
  flag, User/Supervisor flag
• PCD PWT flag, Page size flag
• The 20 MSB of a page frame physical address
• Extended Paging
• Page size 4MB instead of 4KB
• Offset is 22 bits

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Paging in hardware

• Three level Paging
• For 64bit architecture (for example, HP Alpha,
  Itanium)
• Page size 8KB, offset is 13bits long
• Only 43 LSB used 30 bits splits into three
  10-bit fields
• Physical Address Extension (PAE)
• Upto 64GB of RAM
• A new level page table Page Directory Pointer
  table (PDPT)
• 64GB 224 page frames
• Four 64bit entry
• Cr3 contains 27bit PDPT base address

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Paging in hardware

• Hardware Cache
• Reduce the speed mismatch
• Locality principle
• line a few dozen contiguous bytes
• N-way set Associative
• Write-through, write-back
• Table Lookaside Buffers (TLB)
• To speed up linear address translation

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Paging in Linux

• Three Level Paging
• Page global directory, Page middle directory,
  Page table
• in x86 pentium eliminate middle directory
• In later processors use PAE mechanism
• Reserved Page Frames
• For store kernel code data from 0x00100000
• about first 2MB of RAM are filled by Linux
• Process Page Tables
• 0x00000000 0xbfffffff user or kernel mode
• 0xc0000000 0xffffffff kernel mode only