Address Assignment Combined with Scheduling in DSP Code Generation

1
Address Assignment Combined with Scheduling in
DSP Code Generation

• Dept. of Computer Science,
• KAIST, Korea
• Yoonseo Choi and Taewhan Kim

2
Content

• Introduction
• Related Work
• Preliminaries
• Unification of Scheduling and Address Assignment
• Experimental Results
• Conclusion

3
Introduction

• Address Assignment Problem in DSPs
• Optimization of memory layout for program
  variables to reduce address code size
• Importance due to small size of program ROM of
  embedded systems
• Maximizing utilization of auto-increment/decrement
  addressing mode instructions

4
Introduction (cont)

• Address Generation Unit (AGU)

modify register file
AR pointer
1
address register file
To address bus
/ -
5
Related Work

• Liao, et al. 95 Formulation of Simple/General
  offset assignment (SOA/GOA), problem. NP-hard.
• Leupers, Marwedel 96 Tie-breaking heuristic and
  variable partitioning method.
• Geboyts 97 Assigning address registers
  optimally with given memory layout.
• Rao, Pande 99 Utilizing local reordering of
  commutative operands.
• Lim, et al. 01 Utilizing code scheduling
  effects by seeking sparser graphs.

6
Preliminaries

• Access sequence of variables

b f a
1
2
3
order of access
f a b f e a c b g a b g g e b c b d d a d c e g a
a a d e f
Access sequence
Input code
7
Preliminaries (cont)

• Optimal offset assignment (SOA)

Maximum-weighted Path Cover a path cover P that
minimizes,
1
2
a
g
1
3
3
2
f
b
1
1
2
2
3
1
e
c
b
c
d
a
g
e
f
Memory layout
d
1
1
1
Cost 12
8
Unification of Scheduling and Address Assignment

• Impact of code scheduling

f a b c b g e f a a b g g e b c e g c b d d a d
a a a d e f
d
a
f
e
g
b
c
memory layout
rescheduling of operations
of nonzero cost access 7
9
Unification of Scheduling and Address Assignment
(cont)
SOA Problem ( AR 1)

• Two-Step Approach
• Initial Solution
• Refinement

Commutative Operations
10
Phase 1 Generation of Initial Code Schedule

• List scheduling

fedfacedbcedbabcbca
a
d
b
d
-


1
2
3
d
2
b
d
f
c
e

-
2
4
5
1
4
3
g
h
2
2
1
a
c
e
f
1
Dependency Graph Ready Ops 1,2,3
Partial Access Graph
11
Phase 1 Generation of Initial Code Schedule
(cont)
2
0?2
b
d
1
2
4
3
Access graph appended by d a f (op1)
2
2
1
a
c
e
f
1?2
C w(a,d)w(b,d)w(d,f)
w(a,c)w(e,f) 8
12
Phase 1 Generation of Initial Code Schedule
(cont)
2
b
d
2?3
1
4?5
3
2
Access graph appended by a b c (op2)
2
1
a
c
e
f
1
C w(a,c)w(b,d)
w(a,f)w(e,f) 6
13
Phase 1 Generation of Initial Code Schedule
(cont)
2?3
b
d
2?3
1
4
2?3
Access graph appended by b d e (op3)
2
2
1
a
c
e
f
1
C w(a,b)w(c,e)
w(d,f)w(a,f) 7
14
Phase 1 Generation of Initial Code Schedule
(cont)

• After op2 is scheduled

fedfacedbcedbabcbcaabc
a
b
2

d
d
2
b
d
-

1
3
3
1
5
3
e
d
f
c
2
2
1

-
a
c
e
f
4
5
h
g
1
Partial access graph C 6
Dependency Graph Ready Ops 1,3
15
Phase 2 Refinement Schedule Exploration

• Iterative improvement technique
• Necessary to have a fast generation of solution
  for each schedule instance? Exploit the solution
  of previous schedule.

16
Phase 2 Refinement Schedule Exploration

• Rescheduling of an operation

op1
x1
x1
x1
x6
W--
x2
x4
W
op2
x5
x2
W
x6
W--
x3
x3
x2
x7
x4
x5
op3
W--
W
x4
x6
x3
x7
x7
Updating edge weightsin access graph
Rescheduling
17
Schedule-SOA

• Case 1 C(G(V,Eold),Pold) gt C(G(V,Enew),Pold)

2
1
a
e
c
5
2
3
3
1
d
b
4
C (old) 6
Before rescheduling
18
Schedule-SOA

• Case 1 C(G(V,Eold),Pold) gt C(G(V,Enew),Pold)

2?1
2
1
1
a
e
c
a
e
c
5
5
2
2?1
3
3
3
3
apply Pold
1
1?0
d
b
d
b
Pold
4
4?5
C (new) 4 lt 6
C (old) 6
Before rescheduling
After rescheduling
19
Schedule-SOA (cont)

• Case 2 C(G(V,Eold),Pold) C(G(V,Enew),Pold)

2
2?4
1
1
a
e
c
a
e
c
5
5
2
2
3
3
3
3?2
Pold
1?0
1
d
b
d
b
4
4?5
C (old) 6
C (new) 7 gt 6
Before rescheduling
After rescheduling - using Pold
20
Extension Schedule-GOA
V1 a, b, c
V2 d, e, f, g
V3 h, i, j, k
2
a
d
e
h
k
1?0
1?2
2?3
2
1
3
3
3
3
1
b
c
f
g
i
j
2
2
4
C (old) gt C (new)
C (old) C (new)
C (old) lt C (new)
21
Exploiting Operand-Input Commutativity

• For a commutative operations such as
  f a bpossible access orders are
  considered like a b f, b a f

22
Experimental Results - SOA

• SOA results for benchmark designs

23
Experimental Results - GOA

• GOA benchmark results when AR 2

avg. gain 33.3
50
solve-GOA
sch-GOA
40
of address instructions
30
20
10
0
fir
ellip
comp
gauher
gaujac
gauleg
biquad
24
Experimental Results - GOA

• GOA benchmark results when AR 4

avg. gain 20
20
solve-GOA
sch-GOA
16
of address instructions
12
8
4
0
fir
biquad
ellip
comp
gauleg
gauher
gaujac
25
Experimental Results - GOA (cont)

• GOA benchmark results when AR 8

avg. gain 13.9
10
solve-GOA
sch-GOA
7.5
of address instructions
5
2.5
0
biquad
ellip
comp
gauleg
gauher
gaujac
fir
26
Conclusion

• A fast and effective Address assignment technique
  tightly coupled with code scheduling
• SOA, GOA, reordering using Commutativity
• Address code size reduction from 25 to 50 for
  SOA, and from13 to 33 for GOA over fixed
  scheduling technique

27
Further Consideration

• Limitations
• Side effect from the phase coupling
• Small scope of application
• Subset of architecture

28
AGU parameters for different DSPs
TI C25
Motorola 56xxx
ADSP-210x
AMS Gepard
address_reg 8 4
4
8 modify_reg 1 4
4
8 increment/ decrement- 1
1 0
64
29
Effect of case 1 / case 2