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First Results with the QIE8 ASIC

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... S. Los, C. Nelson, T. Shaw, J. Whitmore, R. J. Yarema, T. ... Input Cable. 1% up to 1 mA. CALOR2002, Pasadena, March 25-29, 2002. 7. Inverting Amp/Splitter ... – PowerPoint PPT presentation

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Title: First Results with the QIE8 ASIC


1
First Results with the QIE8 ASIC
  • A. Baumbaugh, J. E. Elias, J. Hoff, S. Los, C.
    Nelson, T. Shaw, J. Whitmore, R. J. Yarema, T.
    Zimmerman
  • Fermi National Accelerator Laboratory
  • P.O. Box 500, Batavia, Illinois 60510
  • Presented by S. Los
  • March 27, 2002

2
Outline
  • Introduction to HCAL Readout
  • QIE requirements/operation
  • QIE8 functional blocks
  • Test-bench measurements
  • Conclusions

3
CMS HCAL Signal Collection
  • QIE is a charge sensitive digitizer located in a
    readout box on or close to the detector.

4
QIE Requirements
  • In this table are the very basic requirements for
    the HCAL digitizer. For comparison there is a
    column with its predecessor data.
  • The most challenging improvements needed are the
    Noise, Sensitivity, and Analog BW (non-inverting
    input for HF PMT).

5
QIE Block Diagram
  • Two Amplifier sets for signals from PMTs/HF and
    HPDs/HBHE
  • Four Integrator sets to cover Compare/MuxOut/Reset
    phases when the first set is not integrating

6
Non-Inverting Amp/Splitter
  • There are two major requirements to process PMT
    signals
  • High bandwidth to integrate the whole signal in a
    25 ns slice, and avoid signal pile-up from other
    beam crossings.
  • Stable input impedance to use transmission
    cables, and remove the electronics from high
    radiation zone.

1 up to 1 mA
7
Inverting Amp/Splitter
  • HPD has a much smaller gain than a PMT, thus we
    needed following
  • Higher sensitivity and lower noise.
  • 40 MHz BW to collect the signal in few time
    slices and provide it with a time stamp .

8
QIE8 FADC Ladder Design
  • There are two structural changes that made it
    possible to meet our requirements of dynamic
    range, sensitivity, and precision while allowing
    to decrease the number of integration ranges from
    8 to 4.
  • Non-linear Ladder design
  • Two comparator sets for Regular/Calibration mode
    operation
  • Regular mode is piece linear with steps 1?, 2?,
    3?, 4?, 5? wide.
  • Calibration mode is linear and uses additional
    taps 1/3 ? on the same ladder.

9
QIE8 Response Function
  • Due to proper biasing every conversion range
    covers a dynamic range of about 51 thus
    preserving precision in the beginning of the
    scale.

10
FADC Quantization Error
  • Implementation of a 4-range splitter and a 5 bit
    non-linear FADC allows to simplify the design
    while having minimum effect on the detector
    resolution.

11
FADC Linearity
  • La

12
FADC Linearity
13
Timing of the Signal
14
Timing of the Signal
15
Calibration Mode DNL
16
2 Channel QIE Board
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