CSEE 3700 : Fundamentals of Digital System Design

1
CS/EE 3700 Fundamentals of Digital System Design

• Chris J. Myers
• Lecture 10 Digital System Design
• Chapter 10

2
Digital System Design

• Digital system consists of two parts
• Datapath circuit used to store, manipulate, and
  transfer date.
• Control circuit controls the operation of the
  datapath. Usually its built using an FSM.

3
E
0
D
Q
Q
R
1
Q
Clock
Figure 10.1 A flip-flop with an enable input
4
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY rege IS PORT ( R, Resetn, E, Clock
IN STD_LOGIC Q BUFFER STD_LOGIC )
END rege ARCHITECTURE Behavior OF rege
IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN Q lt '0' ELSIF
Clock'EVENT AND Clock '1' THEN IF E '1'
THEN Q lt R ELSE Q lt Q END IF
END IF END PROCESS END Behavior
Figure 10.2 VHDL code for a D flip-flop with
an enable input
5
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY regne IS GENERIC ( N INTEGER 4 )
PORT ( R IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Resetn IN STD_LOGIC E, Clock
IN STD_LOGIC Q OUT STD_LOGIC_VECTOR(N-
1 DOWNTO 0) ) END regne ARCHITECTURE
Behavior OF regne IS BEGIN PROCESS ( Resetn,
Clock ) BEGIN IF Resetn '0' THEN Q lt
(OTHERS gt '0') ELSIF Clock'EVENT AND Clock
'1' THEN IF E '1' THEN Q lt R END
IF END IF END PROCESS END Behavior
Figure 10.3 VHDL code for an n-bit register
with an enable input
6
LIBRARY ieee USE ieee.std_logic_1164.all --
right-to-left shift register with parallel load
and enable ENTITY shiftlne IS GENERIC ( N
INTEGER 4 ) PORT( R IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) L, E, w
IN STD_LOGIC Clock IN STD_LOGIC
Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0)
) END shiftlne ARCHITECTURE Behavior OF
shiftlne IS BEGIN PROCESS BEGIN cont
Figure 10.4a Code for a right-to-left shift
register with an enable input
7
cont WAIT UNTIL Clock'EVENT AND Clock
'1' IF E '1' THEN IF L '1' THEN Q
lt R ELSE Q(0) lt w Genbits FOR i
IN 1 TO N-1 LOOP Q(i) lt Q(i-1) END
LOOP END IF END IF END PROCESS END
Behavior
Figure 10.4b Code for a right-to-left shift
register with an enable input (cont)
8
LIBRARY ieee USE ieee.std_logic_1164.all
PACKAGE components IS -- 2-to-1
multiplexer COMPONENT mux2to1 PORT ( w0, w1
IN STD_LOGIC s IN STD_LOGIC
f OUT STD_LOGIC ) END COMPONENT
-- D flip-flop with 2-to-1 multiplexer
connected to D COMPONENT muxdff PORT ( D0, D1,
Sel, Clock IN STD_LOGIC Q OUT
STD_LOGIC ) END COMPONENT -- n-bit
register with enable COMPONENT regne GENERIC
( N INTEGER 4 ) PORT ( R IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) Resetn
IN STD_LOGIC E, Clock IN STD_LOGIC
Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
END COMPONENT cont
Figure 10.5a Component declaration statements
for building blocks
9
cont -- n-bit right-to-left shift register
with parallel load and enable COMPONENT shiftlne
GENERIC ( N INTEGER 4 ) PORT ( R
IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) L, E,
w IN STD_LOGIC Clock IN STD_LOGIC
Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO
0) ) END COMPONENT -- n-bit left-to-right
shift register with parallel load and
enable COMPONENT shiftrne GENERIC ( N
INTEGER 4 ) PORT ( R IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) L, E, w
IN STD_LOGIC Clock IN STD_LOGIC
Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO
0) ) END COMPONENT cont
Figure 10.5b Component declaration statements
for building blocks (cont)
10
cont -- up-counter that counts from 0 to
modulus-1 COMPONENT upcount GENERIC (
modulus INTEGER 8 ) PORT ( Resetn
IN STD_LOGIC Clock, E, L IN
STD_LOGIC R IN INTEGER RANGE 0 TO
modulus-1 Q BUFFER INTEGER RANGE 0
TO modulus-1 ) END COMPONENT --
down-counter that counts from modulus-1 down to
0 COMPONENT downcnt GENERIC ( modulus
INTEGER 8 ) PORT ( Clock, E, L IN
STD_LOGIC Q BUFFER INTEGER RANGE 0
TO modulus-1 ) END COMPONENT END components

Figure 10.5c Component declaration statements
for building blocks (cont)
11
Static Random Access Memory

• SRAM is used when a large amount of data needs to
  be stored.
• SRAM block is 2-dimensional array of SRAM cells
  where each cell stores 1-bit.
• To store m elements of n-bits, the aspect ratio
  of the SRAM array would be m ? n.

12
Figure 10.6 An SRAM cell
13
Data
Data
0
1
Sel
0
Sel
1
Figure 10.7 A 2 x 2 array of SRAM cells
14
d
d
d
Data inputs
0
n
1

n
2

Write
Sel
0
Sel
1
Sel
a
2
0
decoder
a
1
m
Address
-to-2
a
m
m
1

Sel
m
2
1

Read
q
q
q
Data outputs
0
n
1

n
2

Figure 10.8 A 2m x n SRAM block
15
Figure 10.9 Pseudo-code for the bit counter
16
Reset
S1
B
0

Load A
0
0
1
s
s
1
S3
S2
Done
Shift right A
1

A
0

?
B
B
1

0
0
a
0
1
Figure 10.10 ASM chart for the bit counter
17
0
Data
log
n
n
2
w
0
LB
L
L
Counter
LA
EB
E
Shift
E
EA
Clock
log
n
A
2
n
B
z
a
0
Figure 10.11 Data path for the bit counter
18
Reset
S1
,
LB
EB
EA
0
0
0
1
1
s
s
LA
1
S3
S2
EA
Done
1
z
EB
0
0
a
0
1
Figure 10.12 ASM chart for the bit counter
control circuit
19
LIBRARY ieee USE ieee.std_logic_1164.all
LIBRARY work USE work.components.shiftrne
ENTITY bitcount IS PORT( Clock, Resetn IN
STD_LOGIC LA, s IN STD_LOGIC Data
IN STD_LOGIC_VECTOR(7 DOWNTO 0) B
BUFFER INTEGER RANGE 0 to 8 Done OUT
STD_LOGIC ) END bitcount ARCHITECTURE
Behavior OF bitcount IS TYPE State_type IS ( S1,
S2, S3 ) SIGNAL y State_type SIGNAL A
STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL z, EA, LB,
EB, low STD_LOGIC BEGIN FSM_transitions
PROCESS ( Resetn, Clock ) BEGIN IF Resetn
'0' THEN y lt S1 cont
Figure 10.13a VHDL code for the bit-counting
circuit
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ELSIF (Clock'EVENT AND Clock '1')
THEN CASE y IS WHEN S1 gt IF s '0'
THEN y lt S1 ELSE y lt S2 END IF WHEN
S2 gt IF z '0' THEN y lt S2 ELSE y lt S3
END IF WHEN S3 gt IF s '1' THEN y
lt S3 ELSE y lt S1 END IF END CASE
END IF END PROCESS FSM_outputs PROCESS
( y, s, A(0), z ) BEGIN EA lt '0' LB lt '0'
EB lt '0' Done lt '0' CASE y IS WHEN
S1 gt LB lt '1' EB lt '1' IF s '0'
AND LA '1' THEN EA lt '1' ELSE EA lt '0'
END IF WHEN S2 gt EA lt '1' IF
A(0) '1' THEN EB lt '1' ELSE EB lt '0' END
IF cont
Figure 10.13b VHDL code for the bit-counting
circuit (cont)
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WHEN S3 gt Done lt '1' END CASE END
PROCESS -- The datapath circuit is described
below upcount PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN B lt 0
ELSIF (Clock'EVENT AND Clock '1')
THEN IF EB '1' THEN IF LB '1'
THEN B lt 0 ELSE B lt B 1
END IF END IF END IF END
PROCESS low lt '0' ShiftA shiftrne GENERIC
MAP ( N gt 8 ) PORT MAP ( Data, LA, EA, low,
Clock, A ) z lt '1' WHEN A "00000000" ELSE
'0' END Behavior
Figure 10.13c VHDL code for the bit-counting
circuit (cont)
22
Figure 10.14 Simulation results for the
bit-counting circuit
23
Binary
Decimal
Multiplicand
1
0
1
1
13
1
Multiplier
1
0
1

11

1 1 0 1
13
1
0
1
1
13
0
0
0
0
143
1
0
1
1
Product
0
1
0 0 1 1 1 1
(a)
Manual
method
(b)
Pseudo-code
Figure 10.15 An algorithm for multiplication
24
Reset
S1
P
0

Load A
Load B
0
0
1
s
s
1
S3
S2
Shift left A
,
Shift right
B
Done
1
P
P
A


B
0

?
0
0
b
0
1
Figure 10.16 ASM chart for the multiplier
25
Figure 10.17 Datapath circuit for the
multiplier
26
Figure 10.18 ASM chart for the multiplier
control circuit
27
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all USE
work.components.all ENTITY multiply
IS GENERIC ( N INTEGER 8 NN INTEGER
16 ) PORT ( Clock IN STD_LOGIC
Resetn IN STD_LOGIC LA, LB, s
IN STD_LOGIC DataA IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) DataB IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) P
BUFFER STD_LOGIC_VECTOR(NN-1 DOWNTO 0) Done
OUT STD_LOGIC ) END multiply
ARCHITECTURE Behavior OF multiply IS TYPE
State_type IS ( S1, S2, S3 ) SIGNAL y
State_type SIGNAL Psel, z, EA, EB, EP, Zero
STD_LOGIC SIGNAL B, N_Zeros
STD_LOGIC_VECTOR(N-1 DOWNTO 0) SIGNAL A, Ain,
DataP, Sum STD_LOGIC_VECTOR(NN-1 DOWNTO 0)
BEGIN cont
Figure 10.19a VHDL code for the multiplier
circuit
28
FSM_transitions PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN y lt S1
ELSIF (Clock'EVENT AND Clock '1')
THEN CASE y IS WHEN S1 gt IF s '0'
THEN y lt S1 ELSE y lt S2 END IF WHEN
S2 gt IF z '0' THEN y lt S2 ELSE y lt S3
END IF WHEN S3 gt IF s '1' THEN y
lt S3 ELSE y lt S1 END IF END CASE
END IF END PROCESS FSM_outputs PROCESS
( y, s, LA, LB, B(0) ) BEGIN EP lt '0' EA lt
'0' EB lt '0' Done lt '0' Psel lt
'0' CASE y IS WHEN S1 gt EP lt '1'
IF s '0' AND LA '1' THEN EA lt '1'
ELSE EA lt '0' END IF IF s '0' AND
LB '1' THEN EB lt '1' cont
Figure 10.19b VHDL code for the multiplier
circuit (cont)
29
ELSE EB lt '0' END IF WHEN S2
gt EA lt '1' EB lt '1' Psel lt '1'
IF B(0) '1' THEN EP lt '1' ELSE EP lt
'0' END IF WHEN S3 gt Done lt '1'
END CASE END PROCESS -- Define the
datapath circuit Zero lt '0' N_Zeros lt
(OTHERS gt '0' ) Ain lt N_Zeros DataA
ShiftA shiftlne GENERIC MAP ( N gt NN
) PORT MAP ( Ain, LA, EA, Zero, Clock, A )
ShiftB shiftrne GENERIC MAP ( N gt N ) PORT
MAP ( DataB, LB, EB, Zero, Clock, B ) z lt '1'
WHEN B N_Zeros ELSE '0' Sum lt A P --
Define the 2n 2-to-1 multiplexers for
DataP GenMUX FOR i IN 0 TO NN-1
GENERATE Muxi mux2to1 PORT MAP ( Zero, Sum(i),
Psel, DataP(i) ) END GENERATE RegP regne
GENERIC MAP ( N gt NN ) PORT MAP ( DataP,
Resetn, EP, Clock, P ) END Behavior
Figure 10.19c VHDL code for the multiplier
circuit (cont)
30
Figure 10.20 Simulation results for the
multiplier circuit
31
15
Q
00001111
9
140
A
100
01100
1001
B
9
1001
50
10
001
45
10
01
10000
5
1001
1110
1001
(a) An example using decimal numbers
R
101
(b) Using binary numbers
R

0

for
i

0
to
n
1
do

Left-shift
R
??A

?
if
R
B then
q

1

i
R

R
B


else
q

0

i
end
if
end
for
(c)
Pseudo-code
Figure 10.21 An algorithm for division
32
Figure 10.22 ASM chart for the divider
33
0
DataB
n
DataA
LA
EB
Rsel
0
1
n
n
LR
L
E
L
Left-shift
Left-shift
Register
E
ER
w
EA
register
register
E
n
n
n
B
a
n
1

A
EQ
E
Left-shift
c
c
w
1
out
in
register

n
n
Clock
Q
R
Figure 10.23 Datapath circuit for the divider
34
Figure 10.24 ASM chart for the divider control
circuit
35
10001100
1001
A
B
rr
Clock cycle
A/
Q
R
0
Load A, B
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
Shift left
,
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
Shift left
Q
0

0
,
1
1
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Shift left
Q
0

0
,
3
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Shift left
Q
0

0
,
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0

4
Shift left
Q
0
0
,
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0

5
Subtract
Q
1
0
,
6
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
Subtract
Q
1

0
,
7
Subtract
Q
1

0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
,

8
Subtract
Q
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
Figure 10.25 An example of division using n
8 clock cycles
36
Figure 10.26 An example of division using n
8 clock cycles
37
Figure 10.27 Datapath circuit for the enhanced
divider
38
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all USE
work.components.all ENTITY divider IS GENERIC
( N INTEGER 8 ) PORT ( Clock IN
STD_LOGIC Resetn IN STD_LOGIC s,
LA, EB IN STD_LOGIC DataA IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) DataB IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) R, Q
BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) Done
OUT STD_LOGIC ) END divider
ARCHITECTURE Behavior OF divider IS TYPE
State_type IS ( S1, S2, S3 ) SIGNAL y
State_type SIGNAL Zero, Cout, z STD_LOGIC
SIGNAL EA, Rsel, LR, ER, ER0, LC, EC, R0
STD_LOGIC SIGNAL A, B, DataR
STD_LOGIC_VECTOR(N-1 DOWNTO 0) SIGNAL Sum
STD_LOGIC_VECTOR(N DOWNTO 0) -- adder
outputs SIGNAL Count INTEGER RANGE 0 TO N-1
cont
Figure 10.28a VHDL code for the divider circuit
39
BEGIN FSM_transitions PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN y lt S1 ELSIF
(Clock'EVENT AND Clock '1') THEN CASE y
IS WHEN S1 gt IF s '0' THEN y lt S1
ELSE y lt S2 END IF WHEN S2 gt IF z
'0' THEN y lt S2 ELSE y lt S3 END IF
WHEN S3 gt IF s '1' THEN y lt S3
ELSE y lt S1 END IF END CASE END IF
END PROCESS FSM_outputs PROCESS ( s, y,
Cout, z ) BEGIN LR lt '0' ER lt '0' ER0 lt
'0' LC lt '0' EC lt '0' EA lt '0' Done
lt '0' Rsel lt '0' CASE y IS WHEN S1
gt cont
Figure 10.28b VHDL code for the divider
circuit (cont)
40
LC lt '1' EC lt '1' ER lt '1' IF
s '0' THEN LR lt '1' IF LA '1'
THEN EA lt '1' ELSE EA lt '0' END IF
ELSE EA lt '1' ER0 lt '1' END
IF WHEN S2 gt Rsel lt '1' ER lt '1'
ER0 lt '1' EA lt '1' IF Cout '1' THEN
LR lt '1' ELSE LR lt '0' END IF IF z
'0' THEN EC lt '1' ELSE EC lt '0' END IF
WHEN S3 gt Done lt '1' END CASE
END PROCESS -- define the datapath
circuit Zero lt '0' RegB regne GENERIC MAP (
N gt N ) PORT MAP ( DataB, Resetn, EB, Clock, B
) ShiftR shiftlne GENERIC MAP ( N gt N
) PORT MAP ( DataR, LR, ER, R0, Clock, R )
cont
Figure 10.28c VHDL code for the divider
circuit (cont)
41
FF_R0 muxdff PORT MAP ( Zero, A(N-1), ER0,
Clock, R0 ) ShiftA shiftlne GENERIC MAP ( N
gt N ) PORT MAP ( DataA, LA, EA, Cout, Clock, A
) Q lt A Counter downcnt GENERIC MAP (
modulus gt N ) PORT MAP ( Clock, EC, LC, Count
) z lt '1' WHEN Count 0 ELSE '0' Sum lt
R R0 (NOT B 1) Cout lt Sum(N) DataR lt
(OTHERS gt '0') WHEN Rsel '0' ELSE Sum END
Behavior
Figure 10.28d VHDL code for the divider
circuit (cont)
42
Figure 10.29 Simulation results for the
divider circuit
43
Figure 10.30 An algorithm for finding the mean
of k numbers
44
Figure 10.31 Datapath circuit for the mean
operation
45
Figure 10.32 ASM chart for the control circuit
46
Figure 10.33 Schematic of the mean circuit
with an SRAM block
47
Figure 10.34 Simulation results for the mean
circuit using SRAM
48

for
i

0
to
k
2
do
A

R

i

j

i

1
k
1
for
to
do
B

R

j
if
B
lt
A
then
R

B

i
R

A

j
A

R

i
end if

end for
end for
Figure 10.35 Pseudo-code for the sort operation
49
Figure 10.36 ASM chart for the sort operation
50
DataIn
ABmux
n
WrInit
0
1
n
RData
Rin
Rin
Rin
Rin
E
E
E
E
3
2
1
0
R
R
R
R
0
1
2
3
0
1
2
3
Imux
ABData
Bin
Ain
Rd
E
E
n
Clock
DataOut
lt
Bout
1
0
A
B
BltA
Figure 10.37 A part of the datapath circuit
for the sort operation
51
0
2
2
LJ
LI
R
R
L
L
EJ
EI
E
E
Counter
Counter
Q
Q
C
C
i
j
Clock
2
z
k
2


i
2
1
0
Csel
z
k
1


j
Cmux
2
2
RAdd
1
0
Int
Imux
2
y
Rin
0
0
w
w
,
y
Rin
0
1
1
1
y
Rin
2
2
WrInit
y
Rin
En
3
3
Wr
2-to-4 decoder
Figure 10.38 A part of the datapath circuit
for the sort operation
52
Figure 10.39 ASM chart for the control circuit
53
LIBRARY ieee USE ieee.std_logic_1164.all USE
work.components.all ENTITY sort IS GENERIC (
N INTEGER 4 ) PORT ( Clock, Resetn IN
STD_LOGIC s, WrInit, Rd IN STD_LOGIC
DataIn IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) RAdd IN INTEGER RANGE 0 TO 3
DataOut BUFFER STD_LOGIC_VECTOR(N-1
DOWNTO 0) Done BUFFER STD_LOGIC ) END
sort ARCHITECTURE Behavior OF sort IS TYPE
State_type IS ( S1, S2, S3, S4, S5, S6, S7, S8,
S9 ) SIGNAL y State_type SIGNAL Ci, Cj
INTEGER RANGE 0 TO 3 SIGNAL Rin
STD_LOGIC_VECTOR(3 DOWNTO 0) TYPE RegArray IS
ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(N-1 DOWNTO
0) SIGNAL R RegArray SIGNAL RData, ABMux
STD_LOGIC_VECTOR(N-1 DOWNTO 0) SIGNAL Int,
Csel, Wr, BltA STD_LOGIC SIGNAL CMux, IMux
INTEGER RANGE 0 TO 3
Figure 10.40a VHDL code for the sort operation
54
SIGNAL Ain, Bin, Aout, Bout STD_LOGIC
SIGNAL LI, LJ, EI, EJ, zi, zj STD_LOGIC
SIGNAL Zero INTEGER RANGE 3 DOWNTO 0 --
parallel data for Ci 0 SIGNAL A, B, ABData
STD_LOGIC_VECTOR(N-1 DOWNTO 0)
BEGIN FSM_transitions PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN y lt S1
ELSIF (Clock'EVENT AND Clock '1')
THEN CASE y IS WHEN S1 gt IF S '0' THEN
y lt S1 ELSE y lt S2 END IF WHEN
S2 gt y lt S3 WHEN S3 gt y lt S4 WHEN
S4 gt y lt S5 WHEN S5 gt IF BltA '1' THEN
y lt S6 ELSE y lt S8 END IF WHEN S6 gt
y lt S7 WHEN S7 gt y lt S8 WHEN S8
gt IF zj '0' THEN y lt S4 ELSIF zi
'0' THEN y lt S2 ELSE y lt S9 END
IF
Figure 10.40b VHDL code for the sort operation
(cont)
55
WHEN S9 gt IF s '1' THEN y lt S9 ELSE y
lt S1 END IF END CASE END IF END
PROCESS -- define the outputs generated by the
FSM Int lt '0' WHEN y S1 ELSE '1' Done lt
'1' WHEN y S9 ELSE '0' FSM_outputs PROCESS
( y, zi, zj ) BEGIN LI lt '0' LJ lt '0' EI
lt '0' EJ lt '0' Csel lt '0' Wr lt '0'
Ain lt '0' Bin lt '0' Aout lt '0' Bout lt
'0' CASE y IS WHEN S1 gt LI lt '1' EI lt
'1' WHEN S2 gt Ain lt '1' LJ lt '1' EJ
lt '1' WHEN S3 gt EJ lt '1' WHEN S4 gt
Bin lt '1' Csel lt '1' WHEN S5 gt -- no
outputs asserted in this state WHEN S6 gt Csel
lt '1' Wr lt '1' Aout lt '1' WHEN S7 gt
Wr lt '1' Bout lt '1' WHEN S8 gt Ain lt
'1' IF zj '0' THEN EJ lt '1'
ELSE EJ lt '0'
Figure 10.40c VHDL code for the sort operation
(cont)
56
IF zi '0' THEN EI lt '1'
ELSE EI lt '0' END
IF END IF WHEN S9 gt -- Done is
assigned 1 by conditional signal assignment END
CASE END PROCESS -- define the datapath
circuit Zero lt 0 GenReg FOR i IN 0 TO 3
GENERATE Reg regne GENERIC MAP ( N gt N
) PORT MAP ( RData, Resetn, Rin(i), Clock,
R(i) ) END GENERATE RegA regne GENERIC
MAP ( N gt N ) PORT MAP ( ABData, Resetn, Ain,
Clock, A ) RegB regne GENERIC MAP ( N gt N
) PORT MAP ( ABData, Resetn, Bin, Clock, B )
BltA lt '1' WHEN B lt A ELSE '0' ABMux lt A
WHEN Bout '0' ELSE B RData lt ABMux WHEN
WrInit '0' ELSE DataIn OuterLoop upcount
GENERIC MAP ( modulus gt 4 ) PORT MAP ( Resetn,
Clock, EI, LI, Zero, Ci )
Figure 10.40d VHDL code for the sort operation
(cont)
57
InnerLoop upcount GENERIC MAP ( modulus gt 4
) PORT MAP ( Resetn, Clock, EJ, LJ, Ci, Cj )
CMux lt Ci WHEN Csel '0' ELSE Cj IMux lt
Cmux WHEN Int '1' ELSE Radd WITH IMux
Select ABData lt R(0) WHEN 0, R(1) WHEN
1, R(2) WHEN 2, R(3) WHEN OTHERS
RinDec PROCESS ( WrInit, Wr, IMux
) BEGIN IF (WrInit OR Wr) '1' THEN CASE
IMux IS WHEN 0 gt Rin lt "0001" WHEN
1 gt Rin lt "0010" WHEN 2 gt Rin lt
"0100" WHEN OTHERS gt Rin lt "1000"
END CASE ELSE Rin lt "0000" END IF
END PROCESS Zi lt '1' WHEN Ci 2 ELSE '0'
Zj lt '1' WHEN Cj 3 ELSE '0' DataOut lt
(OTHERS gt 'Z') WHEN Rd '0' ELSE ABData END
Behavior
Figure 10.40e VHDL code for the sort operation
(cont)
58
Figure 10.41a Simulation results for the sort
operation
59
Figure 10.41b Simulation results for the sort
operation
60
DataIn
n
WrInit
n
Rin
Rin
Rin
Rin
E
E
E
E
3
2
1
0
Rout
Rout
Rout
Rout
3
2
1
0
n
n
n
n
Bin
Ain
E
E
n
Clock
n
n
A
B
Rd
Aout
lt
DataOut
BltA
Bout
Figure 10.42 Using tri-state buffers in the
datapath circuit
61
Data
Q
D
Clock
Q
E
Figure 10.43 Clock enable circuit
62
0
Data
log
n
n
2
w
0
LB
L
L
Counter
LA
EB
E
Shift
E
EA
Clock
log
n
A
2
n
B
z
a
0
Figure 10.11 Data path for the bit counter
63
ff
ff
ff
ff
ff
ff
ff
ff
Clock
ff
ff
ff
ff
ff
ff
ff
ff
Figure 10.44 An H tree clock distribution
network
64
t
Data
Chip package pin
Data
A
D
Q
Out
B
Clock
t
t
Clock
od
Figure 10.45 A flip-flop in an integrated
circuit
65
Figure 10.46 Flip-flop timing in a chip
66
Asynchronous Inputs to FFs

• Inputs generated asynchronously may violate setup
  and hold times of flip-flops.
• FF may take on a value between 0 and 1.
• This condition is called a metastable state.
• There is no guarantee of how long the circuit
  will persist in this state.
• Care must be taken to reduce the probability of
  having synchronization failure.

67
Data
Data
Q
Q
D
D
(asynchronous)
(synchronous)
Clock
Q
Q
Figure 10.47 Asynchronous inputs
68
V
DD
R
V
DD
S
Data
R
Data
R
R
V
(a) Single-pole single-throw switch
DD
(b) Single-pole double-throw switch with a basic
SR latch
Figure 10.48 Switch debouncing circuit