Kazi ECE 6811

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ECE 681VLSI Design Automation

• Khurram Kazi
• Thanks to Automation press THE button outcomes
  the Chip !!! Reality or Myth

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Fundamental Steps to a Good design

• If you have a good start, the project will go
  smoothly
• Partitioning the Design is a good start
• Partition by
• Functionality
• Dont mix two different clock domains in a single
  block
• Dont make the blocks too large
• Optimize for Synthesis

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Partitioning
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Partitioning Using HDL

• Using Entities and Instantiating such entities
  partitioning is created.

Entity framing_block is Architecture struct
is U1 pattern_match port map (serial_datain,
clk, reset_n .) U2 frame_monitor port map
(par_data, clk, reset_n, data_out.) . . End
struct
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Partitioning during Synthesis
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Using group command in Synopsys (design
compiler)
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Using ungroup command in Synopsys (design
compiler)
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Recommended rules for Synthesis

• When implementing combinatorial paths do not have
  hierarchy
• Register all outputs
• Do not implement glue logic between block,
  partition them well
• Separate designs on functional boundary
• Keep block sizes to a reasonable size
• Separate core logic, pads, clock and JTAG

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Avoid hierarchical combinatorial blocks
The path between reg1 and reg2 is divided between
three different block Due to hierarchical
boundaries, optimization of the combinatorial
logic cannot be achieved Synthesis tools
(Synopsys) maintain the integrity of the I/O
ports, combinatorial optimization cannot be
achieved between blocks (unless grouping is
used).
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Recommend way to handle Combinatorial Paths
All the combinatorial circuitry is grouped in the
same block that has its output connected the
destination flip flop It allows the optimal
minimization of the combinatorial logic during
synthesis Allows simplified description of the
timing interface
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Register all outputs
Simplifies the synthesis design environment
Inputs to the individual block arrive within the
same relative delay (caused by wire delays) Dont
really need to specify output requirements since
paths starts at flip flop outputs. Take care of
fanouts, rule of thumb, keep the fanout to 16
(dependent on technology and components that are
being driven by the output)
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NO GLUE LOGIC between blocks
Due to time pressures, and a bug found that can
be simply be fixed by adding some simple glue
logic. RESIST THE TEMPTATION!!! At this level in
the hierarchy, this implementation will not allow
the glue logic to be absorbed within any lower
level block.
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Separate design with different goals
reg1 may be driven by time critical function,
hence will have different optimization
constraints reg3 may be driven by slow logic,
hence no need to constrain it for speed
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Optimization based on design requirements

• Use different entities to partition design blocks
• Allows different constraints during synthesis to
  optimize for area or speed or both.

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Separate FSM with random logic

• Separation of the FSM and the random logic allows
  you to use FSM optimized synthesis

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Maintain a reasonable block size

• Partition your design such that each block is
  between 1000-10000 gates (this is strictly tools
  and technology dependent)
• Larger the blocks, longer the run time -gt quick
  iterations cannot be done.

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Partitioning of Full ASIC

• Top-level block includes I/O pads and the Mid
  block instantiation
• Mid includes Clock generator, JTAG, CORE logic
• CORE LOGIC includes all the functionality and
  internal scan circuitry

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Synthesis Constraints

• Specifying an Area goal
• Area constraints are vendor/library dependent
  (e.g. 2 input-nand gate, square mils, grid etc)
• Design compiler has the Max Area constraint as
  one of the constraint attributes.

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Timing constraints for synchronous designs

• Define timing paths within the design, i.e. paths
  leading into the design, internal paths and
  design leading out of the design
• Define the clock
• Define the I/O timing relative to the clock

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Define a clock for synthesis

• Clock source
• Period
• Duty cycle
• Defining the clock constraints the internal
  timing paths

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Timing goals for synchronous design

• Define timing constraints for all paths within a
  design
• Define the clocks
• Define the I/O timing relative to the clock

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Constraining input path

• Input delay is specified relative to the clock
• External logic uses some time within the clock
  period and i.e.
• TclkToQ(clock to Q delay) Tw (net delay) -gtAt
  input to B
• Example command for this in synopsys design
  compiler
• Dc_shellgt set_input_delay clock clk 5 (where 5
  represents the input delay)

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Constraining output path

• Output delay is specified relative to the clock
• How much of the clock period does the external
  logic (shown by cloud b) use up?
• Tb Tsetup The amount to be specified as the
  output delay

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Generic statement for input and output delays

• Normally the input and the output delay values
  are set by using some rule of thumb value which
  is dependent on the fanout, external logic, and
  the technology being used
• The design compiler (Synthesis tools have to work
  with time (Tclk-Tin-Tout) during synthesis.

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False and Multicycle paths

• False path
• Very slow signals like reset test mode enable,
  that are not used under normal conditions are
  classified as false paths
• Multicycle path
• Paths that take more than one clock cycle are
  known as multicycle paths.
• Have to take define the multicylce paths in the
  analyzer and it takes those constraints into
  account when synthesizing

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Example of SONET Framing block in a framer ASIC
1 2 3 4 5 .. . 90th byte
A1
A2
1 2 3 4 5 6 7 8 9
A1 hexF6, A2 hex28 is the framing pattern
used in SONET networks Order or transmission is
F6 (11110110) msb transmitted first. All bytes
other than A1 and A2 are scrambled
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Scrambling in SONET (STS-1)1 x6 x7

• 1234567 datain dataout unscrambled data
• 1 1111111 1 0 1
• 2 0111111 1 0 1
• 3 0011111 0 1 0
• 4 0001111 0 1 0
• 5 0000111 0 1 0
• 6 0000011 1 0 1
• 7 0000001 1 0 1
• 8 1000000 1 1 1
• 9 0100000 1 1 1
• 10 0010000 0 0 0
• 11 0001000 0 0 0

On the receive side use the same circuit and the
receive data goes in the datain pin and the
original unscrambled data is extracted on
dataout
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PRBS (Pseudo Random Binary Sequence)

• PRBS is a very powerful pattern generator and
  that can be self- checking on the receiving end.
• Some of the widely used polynomials are

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BIP -8 (bit interleaved parity) first byte in 2
row, B1 byte

• The BIP-8 (B1 byte) performs even-parity check on
  the previous STS-1 frame, after it has been
  scrambled. The parity is then inserted in the B1
  position in the SONET frame. During the parity
  checking, the first bit of the BIP-8 field is set
  so that the total number of ones in the first
  positions of all the octets in the previously
  scrambled frame is always even number. The bit of
  the BIP-8 is used exactly the same way except it
  performs a check on the second bits of each octet
  and so on.

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Data Com bytes (D1-D3)

• D1-D3 bytes are the 1st three bytes in the 3rd
  row of the STS-1 frame. These bytes are used as a
  192 kbps data channel for operations functions,
  such as Operations, Adminstration, Management and
  Provisioning (OAMP). These bytes are used
  between 2 section type equipment (like
  regenerator)

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Data Com bytes D4-D12

• These bytes (1st three bytes of rows 6,7 and 8)
  represent a 576 kbps message-based channel used
  for OAMP messages between SONET line-level
  network equipment.

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Assignment 1 continued

• Use the SONET scramble to scramble the data
  (except A1 and A1 bytes)
• Calculate B1and insert it in the next SONET frame
• Use PRBS pattern generator to insert in the 3
  Data Com bytes D1-D3 byte positions
• Take first 9 characters of your name and convert
  them into ASCII (bit value). Insert those values
  in the D4-D12 byte positions.
• The D1-D3 and D4-D12 data should come out on
  separate serial ports along with 192 kbps and 576
  kbps clock. The firs byte should be indicated by
  a start of frame signal. (3 ports per Data com
  bytes should be output ports from your block,
  therefore total of 6 output ports)

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Some recommendation for test benches

• Use global signals to pass information between
  the generator to the data analyzer. These global
  signals can be used to control the pattern
  generators as the simulation progress.
• Use some sort of timestamp to keep track of
  events. For example use frame counter (in the
  test bench) to keep track of data sent a
  particular frame and use that information during
  the self checking of the output data!