NoCIC NoC Interconnect Calculator

1
NoCIC NoC Interconnect Calculator

• Feasibility Review (3/26)
• Hempraveen Kukkamalla
• Jinwook Jang
• Vishak Venkatraman
• Zhi Zhu
• ECE 659 Advanced VLSI Design Principles
• http//www-unix.ecs.umass.edu/vvenkatr/ECE659/ind
  ex.html

2
Interconnect Scaling

• Interconnect scaling slows down performance
• reduces the bottleneck by pipelining.
• Interconnect between the latches has considerable
  delay.
• Voltage mode signaling not effective in improving
  delay.
• Need for exploration of new circuit techniques.

Image taken from Andrew Laffelys Webpage.
3
NoCIC NoC Interconnect Calculator

• A Web based, Interactive user-enabled, NoC
  parameterized, delay and power measurement
  system.
• User selects a range of parameters, outputs plots
  on delay, power versus parameters.
• Tile size
• Wire Parameters ( Size, k)
• Technology
• Bus Size
• Signaling
• Clock and Voltage
• Analysis of NoC interconnects with various
  signaling techniques
• Voltage Mode Signaling
• Boosters
• Differential Current Sensing
• Multi-level Current Signaling
• Phase Coding

4
Methodology

• Generation of Delay and power models versus line
  length
• Vary above models with technology, vdd, clock.
• Repeat the process with the various signaling
  techniques.
• Voltage mode signaling
• Differential Current Sensing
• Multi-Level Current Signaling
• Boosters
• Phase coding
• Create a database with all the values
• Create web page using JavaScript
• Map database to user entered values
• Create plots using a appropriate package
  (gnuplot).

5
Where we are

• Simulation of the various Signaling methods.
• Automation using Perl
• Generation of Delay Models
• Variation of Parameters and repeating the above
• Creating an exhaustive database with delay,
  power, line length for various combinations in
  the design space.
• Database completion
• Web creation using JavaScript
• Debugging
• Uploading on the Internet

Simulation
PERL Automation
Completed work
Model Generation
Param Variation
Database Creation
Web Creation
Remaining work
Debugging
Uploading
6
Who did what
7
Differential current Sensing
Interconnect line with DCS Amplifier
Differential Current Sense Amplifier
Simulation Waveform showing Inputs and Outputs
8
Plots for DCS
Line Length Vs Average Power
Line Length Vs Delay
9
Multi-Level current Signaling
Interconnect line with driver
NMOS Current Comparator
Decoder
PMOS Current Comparator
10
MLC Signaling Simulation Waveforms
Current Levels
Delay
11
Voltage Mode Signaling

• For a wire with k repeaters each of size h times
  minimum size inverter is given by
• By setting dT/dk 0 and dT/dh 0, optimal
  values for k and h are obtained

Line Length Vs Delay
12
Phase Coding (Some Problematic Issues)

• PCPWM Encoder Block
• DLL
• Transition Detector
• Encoder
• Integration
• PCPWM Decoder Block
• DLL
• Shifter
• Decoder
• Integration

13
Phase Coding (Possible Design Flow)

• Strong Point
• Faster than Schematic only approach
• Flexible design
• Weak Point
• Logic optimization

14
Boosters
The setup of the Simulation
Booster Circuit
5pi Interconnect model
15
Boosters Simulation
Output of with and without Booster
Inputs and Internal Nodes
16
Schedule

• April 4 Completed database generation, course
  homepage
• April 20 finish work on mapping and coding the
  website in JavaScript.
• April 22 Implementation review
• May 1 finish debugging (hopefully) and
  uploading the website and trial run
• May 6 Integration Review

Work split up

• Lead Programmers in JavaScript are Vishak and
  Jinwook
• Support in programming and database handling by
  Hem and Zhu

17
Conclusions

• Simulation of the various Signaling methods.
• Automation using Perl
• Generation of Delay Models
• Variation of Parameters and repeating the above
• Creating an exhaustive database with delay,
  power, line length for various combinations in
  the design space.

18
References

• J. Liang, S. Swaminathan, and R. Tessier, aSOC A
  Scalable, Single-Chip Communications
  Architecture, in the Proceedings of the
  IEEEInternational Conference on Parallel
  Architectures and Compilation
• Techniques (PACT), Philadelphia, PA.
  October 2000.
• http//vsp2.ecs.umass.edu/vspg/ASOC/Projects_Page/
  project.html. aSoC, Adaptive System on a Chip web
  site.
• Sylvester D. and Keutzer K., "Getting to the
  botthon of deep submicron II A Global
  Paradigm", Proceedings on IEEE symposium on
  Physical Design,1999, pp. 193-200
• Bakoglu H.B., " Circuits, Interconnections and
  Packaging for VLSI",Addison Wesley, 1990
• Atul Maheshwari and Wayne Burleson,
  Current-sensing for Global Interconnects,
  Secondary Design Issues Analysis and Solutions,
  IEEE International Workshop on power and timing
  modeling, optimization and simulation, 2001
• Multi-bit Signaling, chapter 3, 4 from the
  Master's Dissertation by Sriram Srinivasan.
• Phase Coding for Global On-chip Interconnects, a
  technical report by Mandeep Singh
• Ankireddy Namalpu and Wayne Burleson, A Practical
  Apporach to DSM Repeater Insertion Satifying
  Delay Constraints while Minimizing Area and
  Power, IEEE ASIC SOC Conference, 2001
• Manoj Sinha and Wayne Burleson, Current-Sensing
  for Crossbars, IEEE ASIC SOC Conference, 2001
• Atul Maheshwari, Srividya Srinivasaraghavan and
  Wayne Burleson, Quantifying the Impact of
  Current-Sensing on Interconnect Delays Trends,
  IEEE ASIC SOC Conference, 2002
• Srividya Srinivasaraghavan and Wayne Burleson,
  Interconnect Effort - A Unification of Repeater
  Insertion and Logical Effort, IEEE International
  Symposium on VLSI, 2003