ASPH CRM Interface

1
ASP/H CRM Interface
John DeHartApplied Research LaboratoryComputer
Science and Engineering Departmenthttp//www.arl.
wustl.edu/arl/projects/techX
2
Advanced Services Card
RDRAM
Power
ACE
DDR SDRAM
DDR SDRAM
QDR
QDR
QDR
QDR
Power
ASP/H-1P100
40?625(160 pins)
QDR
QDR
5
DDR SDRAM
GPIO
ASP/S2850
CRMP100
Rocket IO
QDR
10 x 2.5G
16? lt700 (64 pins)
10
RDRAM
PCI Bus Signals (for control only)
DDR SDRAM
DDR SDRAM
ASP/H-2P100
GPIO
10/100 Connector
QDR
5
RDRAM
Power
40?625(160 pins)
Power
Ethernet PHY
Power
QDR
QDR
QDR
QDR
3
Interface
External
FPGA
40
RDat_P
40
256
RDat_N
SnkData2550
Sink
RDClk_P
SnkClk 125MHz
RDClk_N

• RDClk lt 312.5 MHz (625 Mbps)
• 40 625 Mbps 25Gbps
• SnkClk 125 MHz
• 256 125 Mbps 32 Gbps
• Ample to keep up with External rate

4
ASP-H CRM Interface Specs

• Full 25 Gb/s Data bus
• 40 Data Signals (160 pins)
• bidirectional (x2)
• differential (x2)
• 625 Mb/s per data signal
• using DDR double clock edge ? 312.5 MHz clock
• Trimmed down ASC Data bus
• handle 5 Rocket IOs worth of data
• 5 2.5 Gb/s 12.5 Gb/s
• 40 Data Signals (160 pins)
• 312.5 Mb/s per data signal
• using DDR double clock edge ? 156.25 MHz clock

5
ASP-H CRM Interface Specs (continued)

• Should we consider using something like SPI-4.2?
• 16 bits wide, we would need 2 per ASP/H
• 16 bit bus 700 MHz ? 11.2 Gb/s
• close to trimmed down version of CRM
• 32 bit bus 700 MHz ? 22.4 Gb/s
• close to full version of CRM
• Resource usage of EACH Xilinx SPI-4.2 core is an
  issue
• 14 Block RAMs (V2P100 444)
• 4100 Slices (V2P100 44096)
• 7 Global Clock Buffers (V2P100 16)
• these can possibly be shared among multiple SPI
  cores
• 3 Digital Clock Managers (V2P100 12)
• these can possibly be shared among multiple SPI
  cores

6
ASP/H CRM Interface Resource Usage Summary

• ?? Block Rams (VIIP100 total 444)
• ?? Slices (2VP100 total 44096)
• ?? Global Clock Buffers (2VP100 total 16
• ?? Digital Clock Managers (2VP100 total 12)
• ?? Pins