Simulation of SubMicron Thermal Transport in Emerging Electronics

1
Simulation of Sub-Micron Thermal Transport in
Emerging Electronics

• Jayathi Y. Murthy
• School of Mechanical Engineering
• Purdue University

2
Outline

• Review of phonon transport
• Models based on Boltzmann Transport Equation
  (BTE)
• Concurrent simulation of emerging electronics
• Electro-thermal co-design of circuits
• Future directions and closure

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Sub-micron Heat Conduction
Phonons are quanta of lattice vibrations. They
are the main carriers of energy in semiconductors
and dielectrics.
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Heat Transport in Solids
One-dimensional spring-mass system
Dispersion relation for crystal vibrations,
Majumdar (1998)
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Heat Transport in Solids
Boltzmann transport equation for phonons
Ballistic term
Phonons are characterized by (r, t, K) and
polarization
Frequency vs. reduced wave number in (100)
direction for silicon
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Scattering Processes

• Phonons scatter on impurities, grain boundaries,
  isotopes, physical boundaries, other phonons and
  carriers
• Three-phonon interactions are major contributors
  to thermal resistance at room temperature in
  silicon
• Three-phonon interactions must satisfy momentum
  and energy conservation rules

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Three-Phonon Interactions

• General scattering term for 3-phonon processes
  very complex

Valid only for phonons satisfying conservation
rules
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Relaxation Time Approximation
Bose-Einstein distribution function
Relaxation time
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Silicon on Insulator (SOI) Devices

• Si thermal conductivity 150 W/mK
• SiO2 thermal conductivity 1 W/mK self
  heating
• Max temperature depends on balance between
  generation and transport

Courtesy IBM
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Models based on BTE

• BTE in relaxation time approximation incapable of
  transferring energy across frequencies and
  polarizations
• Too expensive at present to solve full BTE,
  though work is in progress
• Approximations to BTE using relaxation-time form
  as a model

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BTE Models

• Gray BTE
• Semi-gray BTE

Propagation mode
Reservoir mode
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Full-Dispersion Model

• Divide polarization branches into bands
• BTE solved for each band
• All optical bands grouped into single band with
  zero velocity
• Bulk dispersion curve for silicon (100) direction
  is assumed
• Dispersion curve assumed to be isotropic

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Optical Mode BTE
Electron-phonon energy source
Energy exchange due to scattering with jth
acoustic mode
No ballistic term no transport
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Acoustic Mode BTE
Scattering to same band
Ballistic term
Energy exchange with other bands
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Properties of Full-Dispersion Model

• In acoustically-thick limit, full dispersion
  model
• Recovers Fourier conduction in steady state
• Parabolic heat conduction in unsteady state

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Silicon Bulk Thermal Conductivity
Full-Dispersion Model
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Thermal Conductivity of Undoped Silicon Thin
Films

• Experimental data is from Asheghi et. al (1998,
  2002)
• For the numerical results, a specularity
  parameter p0.4 is used

Full-Dispersion Model
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Thermal Conductivity of Doped Silicon Thin Films

• 3.0 micron boron-doped silicon thin films.
  Experimental data is from Asheghi et. al (2002)
• p0.4 is used for numerical predictions
• Boron dopings of 1.0e24 and 1.0e25 atoms/m3
  considered

Full-Dispersion Model
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Multi-Finger PD/SOI nMOSFET
Metallization Layers
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Computational Domain

• 0.15 mW/?m heat source in channel
• Only one active finger

Silicon device layer (BTE region)
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Temperature Predictions Full-Dispersion
Channel
Max temperature 332K
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Comparison of Models
Fourier max temp313.25 K
Gray max temp 320.85K
Semi-gray max temp 456.31 K
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Temperature Comparison
Experimental measurement of temperature rise
13K on top of poly-gate
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What Phonons Responsible for Transport?
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Nanotube Bundle (NTB) TFTs for Macroelectronics
Schematic of Computation Domain
Typical NTB thin film transistor
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Overall Physics

• For zero substrate-tube and tube-tube contact,
  network conductance determined by number of
  bridging tubes

Tube-tube and tube-substrate contact allow
conduction even if LC LS
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Network Conductance
n -1.0
n -1.0
n -1.8
High Tube-Tube Contact (CNT)
Low Tube-Tube Contact (Nanowires)
Bic 5.0, Bis 0.0
Bic 10-5, Bis 0.0

• Linear dependence for high CNT densities
• Non-linear dependence for low CNT densities
• ( close to percolation threshold)

.
Experimental data E. S. Snow et al., Appl. Phys.
Lett. 82(13), 2145 (2003).
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Substrate-Tube Contact Conductance Effect

• Sharp increase in Keff for small Lc
• Thermal conduction dominated by network
  conductance
• Keff achieves invariance beyond LC/Lt 6
• Tube network could provide pathway for heat
  removal for percolating network with high
  tube-tube contact

LC/Lt 2.0, H/Lt 2, Bic 10.0, Ks/Kt 0.001
and ? 10.0 (? 2.5 ?m-2 )
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Tube-Tube Contact Conductance Effect

• Keff achieves invariance beyond LC/Lt 6
• For tube densities higher than the percolation
  threshold, BiC emerges as an important parameter

LC/Lt 2.0, H/Lt 2, Bis 10 -5, Ks/Kt 0.001
and ? 10.0 (? 2.5 ?m-2 )
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Conductivity Ratio Effect

• Percolating conduction dominates for low
  Ks/Kt10-3
• For high values of Ks/Kt, network conductance
  ceases to be a dominant contributor and the
  increase in Keff over Ks drops to zero
• In this limit, large surface area of contact
  between tubes and substrate allows heat to leak
  from network to substrate.

LC/Lt 2.0, H/Lt 2, Bic 10.0, Bis 10-5
and ? 10.0 (? 2.5 ?m-2 )
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Thermally-Aware Circuit Design

• High chip temperatures and gradients have
  serious consequences for transistor and circuit
  performance
• Every 10 C rise decreases drive current by 4
  and increases interconnect delay by 5
• Leakage power depends exponentially on
  temperature
• Objective is to directly integrate thermal
  analysis with circuit design
• Cooling devices operate at the level of 1000s of
  transistors.
• Multiscale simulation allows evaluation/optimizat
  ion of spot-cooling designs for circuit
  performance

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Gate Level Compact Models
Transistor Level FinFET
Compact thermal model of NOR gate
NOR gate composed of PMOS and NMOS FinFETs
Detailed thermal model of NOR gate
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Multiscale Simulation
Spot cooling device ion drag cooling
Compact model
Cell and face heat balances yield coupled
equation set for cell temperatures
Cooling devices may be included in thermal floor
plan
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Dynamic Power and Temperature Maps
Alu4 benchmark circuit
X3 benchmark circuit
Each benchmark circuit contains about 900 gates
and about 3000-4000 transistors
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Closure

• Models for sub-micron thermal transport are being
  developed
• Focus on models based on the BTE
• Inclusion of polarization and dispersion effects
• Accurate computation of scattering terms
• Phonon confinement effects
• Electro-thermal simulation in emerging
  macroelectronics promises improved understanding
  of nano-composites, interface effects.
• Electro-thermal co-design of circuits promises
  better thermal performance and a longer lease of
  life for Moores Law.

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Acknowledgments

• Funding from IBM,NSF, DARPA, Purdue Research
  Foundation
• Students S. Narumanchi, T. Wang, J. Gutierrez,
  C. Ni, S. Kumar, S. Lin
• Collaborators R. Joshi, C-T. Chuang (IBM), S.
  Kang (Aavid), M.A. Alam (Purdue), U. Ravaioli
  (UIUC)